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library: xilinx: versal_xcvr_subsystem: Add LCPLL and ILO reset logic
The first time the board is powered on, because the reference clock going to the transceivers is not stable until the clock chip is programmerd, the LCPLLs are being locked wrong and the master reset controller inside the QUADs gets stuck. The fix is to manually reset the LCPLLs and ILOs inside the QUAD after the clock chip is programmed. Signed-off-by: Bogdan Luncan <[email protected]>
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‎library/xilinx/scripts/versal_xcvr_subsystem.tcl‎

Lines changed: 60 additions & 16 deletions
Original file line numberDiff line numberDiff line change
@@ -84,7 +84,7 @@ proc create_xcvr_subsystem {
8484
dict set phy_params CONFIG.REG_CONF_INTF {AXI_LITE}
8585
dict set phy_params CONFIG.NO_OF_QUADS ${num_quads}
8686
dict set phy_params CONFIG.NO_OF_INTERFACE {1}
87-
dict set phy_params CONFIG.LOCATE_BUFG {CORE}
87+
dict set phy_params CONFIG.LOCATE_BUFG {EXAMPLE_DESIGN}
8888
dict set phy_params CONFIG.INTF0_PRESET ${transceiver}-JESD204_${jesd_mode}
8989
dict set phy_params CONFIG.INTF0_GT_SETTINGS(LR0_SETTINGS) ${xcvr_param}
9090
if {$direction != "RXTX"} {
@@ -163,6 +163,17 @@ proc create_xcvr_subsystem {
163163
}
164164
}
165165

166+
for {set i 0} {$i < $no_lanes} {incr i} {
167+
set quad_idx [expr $i / 4]
168+
set lane_idx [expr $i % 4]
169+
170+
dict set phy_params "CONFIG.QUAD${quad_idx}_CH${lane_idx}_ILORESET_EN" {true}
171+
dict set phy_params "CONFIG.QUAD${quad_idx}_HSCLK0_LCPLLRESET_EN" {true}
172+
dict set phy_params "CONFIG.QUAD${quad_idx}_HSCLK1_LCPLLRESET_EN" {true}
173+
dict set phy_params "CONFIG.QUAD${quad_idx}_HSCLK0_LCPLL_LOCK_EN" {true}
174+
dict set phy_params "CONFIG.QUAD${quad_idx}_HSCLK1_LCPLL_LOCK_EN" {true}
175+
}
176+
166177
# dict for {k v} $phy_params {puts "$k : $v"}
167178
set_property -dict $phy_params [get_bd_cells ${ip_name}]
168179
}
@@ -246,8 +257,12 @@ proc create_versal_jesd_xcvr_subsystem {
246257

247258
create_bd_intf_pin -mode Master -vlnv xilinx.com:display_jesd204:jesd204_rx_bus_rtl:1.0 ${ip_name}/rx${j}
248259
ad_connect ${ip_name}/rx${j} ${ip_name}/rx_adapt_${j}/RX
249-
ad_connect ${ip_name}/rx_adapt_${j}/usr_clk ${ip_name}/xcvr/INTF${rx_intf}_rx_usrclk
260+
ad_connect ${ip_name}/rx_adapt_${j}/usr_clk ${ip_name}/bufg_gt_rx/usrclk
250261
ad_connect ${ip_name}/rx_adapt_${j}/en_char_align ${ip_name}/en_char_align
262+
263+
set quad_idx [expr $j / 4]
264+
set lane_idx [expr $j % 4]
265+
ad_connect ${ip_name}/xcvr/QUAD${quad_idx}_RX${lane_idx}_usrclk ${ip_name}/bufg_gt_rx/usrclk
251266
}
252267
}
253268

@@ -272,12 +287,18 @@ proc create_versal_jesd_xcvr_subsystem {
272287

273288
create_bd_intf_pin -mode Slave -vlnv xilinx.com:display_jesd204:jesd204_tx_bus_rtl:1.0 ${ip_name}/tx${j}
274289
ad_connect ${ip_name}/tx${j} ${ip_name}/tx_adapt_${j}/TX
275-
ad_connect ${ip_name}/tx_adapt_${j}/usr_clk ${ip_name}/xcvr/INTF${tx_intf}_tx_usrclk
290+
ad_connect ${ip_name}/tx_adapt_${j}/usr_clk ${ip_name}/bufg_gt_tx/usrclk
291+
292+
set quad_idx [expr $j / 4]
293+
set lane_idx [expr $j % 4]
294+
ad_connect ${ip_name}/xcvr/QUAD${quad_idx}_TX${lane_idx}_usrclk ${ip_name}/bufg_gt_tx/usrclk
276295
}
277296
}
278297

279298
# Reset signals
280299
create_bd_pin -dir I ${ip_name}/gtreset_in
300+
create_bd_pin -dir I ${ip_name}/gt_lcpllreset_in
301+
create_bd_pin -dir O ${ip_name}/gt_lcpllreset_done
281302
create_bd_pin -dir O ${ip_name}/gtpowergood
282303
if {$intf_cfg != "TX"} {
283304
create_bd_pin -dir I ${ip_name}/gtreset_rx_pll_and_datapath
@@ -290,15 +311,9 @@ proc create_versal_jesd_xcvr_subsystem {
290311
create_bd_pin -dir O ${ip_name}/tx_resetdone
291312
}
292313

293-
create_bd_cell -type module -reference sync_bits ${ip_name}/gtreset_sync
294-
ad_connect ${ip_name}/s_axi_clk ${ip_name}/gtreset_sync/out_clk
295-
ad_connect ${ip_name}/s_axi_resetn ${ip_name}/gtreset_sync/out_resetn
296-
ad_connect ${ip_name}/gtreset_in ${ip_name}/gtreset_sync/in_bits
297-
298-
299-
ad_connect ${ip_name}/gtreset_sync/out_bits ${ip_name}/xcvr/INTF${rx_intf}_rst_all_in
314+
ad_connect ${ip_name}/gtreset_in ${ip_name}/xcvr/INTF${rx_intf}_rst_all_in
300315
if {$rx_intf != $tx_intf} {
301-
ad_connect ${ip_name}/gtreset_sync/out_bits ${ip_name}/xcvr/INTF${tx_intf}_rst_all_in
316+
ad_connect ${ip_name}/gtreset_in ${ip_name}/xcvr/INTF${tx_intf}_rst_all_in
302317
}
303318

304319
foreach port {pll_and_datapath datapath} {
@@ -307,14 +322,43 @@ proc create_versal_jesd_xcvr_subsystem {
307322
continue
308323
}
309324
set intf [expr {$rx_tx == "rx" ? $rx_intf : $tx_intf}]
310-
create_bd_cell -type module -reference sync_bits ${ip_name}/gtreset_${rx_tx}_${port}_sync
311-
ad_connect ${ip_name}/s_axi_clk ${ip_name}/gtreset_${rx_tx}_${port}_sync/out_clk
312-
ad_connect ${ip_name}/s_axi_resetn ${ip_name}/gtreset_${rx_tx}_${port}_sync/out_resetn
313-
ad_connect ${ip_name}/gtreset_${rx_tx}_${port} ${ip_name}/gtreset_${rx_tx}_${port}_sync/in_bits
314-
ad_connect ${ip_name}/gtreset_${rx_tx}_${port}_sync/out_bits ${ip_name}/xcvr/INTF${intf}_rst_${rx_tx}_${port}_in
325+
ad_connect ${ip_name}/gtreset_${rx_tx}_${port} ${ip_name}/xcvr/INTF${intf}_rst_${rx_tx}_${port}_in
315326
}
316327
}
317328

329+
ad_ip_instance ilconcat ${ip_name}/lcplllock_concat
330+
ad_ip_parameter ${ip_name}/lcplllock_concat CONFIG.NUM_PORTS [expr 2 * $num_quads]
331+
332+
for {set i 0} {$i < $num_quads} {incr i} {
333+
if {$intf_cfg != "RX"} {
334+
ad_connect ${ip_name}/gtreset_tx_pll_and_datapath ${ip_name}/xcvr/QUAD${i}_hsclk0_lcpllreset
335+
ad_connect ${ip_name}/gtreset_tx_pll_and_datapath ${ip_name}/xcvr/QUAD${i}_hsclk1_lcpllreset
336+
} else {
337+
ad_connect ${ip_name}/gtreset_rx_pll_and_datapath ${ip_name}/xcvr/QUAD${i}_hsclk0_lcpllreset
338+
ad_connect ${ip_name}/gtreset_rx_pll_and_datapath ${ip_name}/xcvr/QUAD${i}_hsclk1_lcpllreset
339+
}
340+
ad_connect ${ip_name}/xcvr/QUAD${i}_hsclk0_lcplllock ${ip_name}/lcplllock_concat/In[expr 2 * $i]
341+
ad_connect ${ip_name}/xcvr/QUAD${i}_hsclk1_lcplllock ${ip_name}/lcplllock_concat/In[expr 2 * $i + 1]
342+
}
343+
344+
ad_ip_instance ilreduced_logic ${ip_name}/lcplllock_and
345+
ad_ip_parameter ${ip_name}/lcplllock_and CONFIG.C_SIZE [expr 2 * $num_quads]
346+
ad_ip_parameter ${ip_name}/lcplllock_and CONFIG.C_OPERATION {and}
347+
348+
ad_connect ${ip_name}/lcplllock_concat/dout ${ip_name}/lcplllock_and/Op1
349+
350+
ad_ip_instance ilvector_logic ${ip_name}/lcplllock_not
351+
ad_ip_parameter ${ip_name}/lcplllock_not CONFIG.C_SIZE {1}
352+
ad_ip_parameter ${ip_name}/lcplllock_not CONFIG.C_OPERATION {not}
353+
354+
ad_connect ${ip_name}/lcplllock_not/Op1 ${ip_name}/lcplllock_and/Res
355+
356+
for {set i 0} {$i < [expr 4 * $num_quads]} {incr i} {
357+
set quad_idx [expr $i / 4]
358+
set lane_idx [expr $i % 4]
359+
ad_connect ${ip_name}/lcplllock_not/Res ${ip_name}/xcvr/QUAD${quad_idx}_ch${lane_idx}_iloreset
360+
}
361+
318362
ad_connect ${ip_name}/xcvr/gtpowergood ${ip_name}/gtpowergood
319363
if {$intf_cfg != "TX"} {
320364
ad_connect ${ip_name}/xcvr/INTF${rx_intf}_rst_rx_done_out ${ip_name}/rx_resetdone

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