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bluncanbluncan
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projects: ad9081_fmca_ebz: versal: Expose LCPLL reset to axi_gpio
Signed-off-by: Bogdan Luncan <[email protected]>
1 parent 41182fe commit 11102fd

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5 files changed

+42
-27
lines changed

5 files changed

+42
-27
lines changed

‎projects/ad9081_fmca_ebz/common/ad9081_fmca_ebz_bd.tcl‎

Lines changed: 8 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -206,6 +206,8 @@ if {$ADI_PHY_SEL == 1} {
206206
create_bd_port -dir O gt_powergood
207207
create_bd_port -dir O rx_resetdone
208208
create_bd_port -dir O tx_resetdone
209+
create_bd_port -dir I gt_lcpllreset
210+
create_bd_port -dir O gt_lcpllresetdone
209211

210212
switch $INTF_CFG {
211213
"RXTX" {
@@ -223,6 +225,8 @@ if {$ADI_PHY_SEL == 1} {
223225
ad_connect ${rx_phy}/gtreset_tx_pll_and_datapath gt_reset_tx_pll_and_datapath
224226
ad_connect ${rx_phy}/rx_resetdone rx_resetdone
225227
ad_connect ${rx_phy}/tx_resetdone tx_resetdone
228+
ad_connect ${rx_phy}/gt_lcpllreset_in gt_lcpllreset
229+
ad_connect ${rx_phy}/gt_lcpllreset_done gt_lcpllresetdone
226230
}
227231
"RX" {
228232
create_versal_jesd_xcvr_subsystem jesd204_phy_rx $JESD_MODE $RX_NUM_OF_LANES 0 $RX_LANE_RATE $TX_LANE_RATE $REF_CLK_RATE $TRANSCEIVER_TYPE $INTF_CFG
@@ -235,6 +239,8 @@ if {$ADI_PHY_SEL == 1} {
235239
ad_connect ${rx_phy}/gtreset_rx_datapath gt_reset_rx_datapath
236240
ad_connect ${rx_phy}/gtreset_rx_pll_and_datapath gt_reset_rx_pll_and_datapath
237241
ad_connect ${rx_phy}/rx_resetdone rx_resetdone
242+
ad_connect ${rx_phy}/gt_lcpllreset_in gt_lcpllreset
243+
ad_connect ${rx_phy}/gt_lcpllreset_done gt_lcpllresetdone
238244
}
239245
"TX" {
240246
create_versal_jesd_xcvr_subsystem jesd204_phy_tx $JESD_MODE 0 $TX_NUM_OF_LANES $RX_LANE_RATE $TX_LANE_RATE $REF_CLK_RATE $TRANSCEIVER_TYPE $INTF_CFG
@@ -247,6 +253,8 @@ if {$ADI_PHY_SEL == 1} {
247253
ad_connect ${tx_phy}/gtreset_tx_datapath gt_reset_tx_datapath
248254
ad_connect ${tx_phy}/gtreset_tx_pll_and_datapath gt_reset_tx_pll_and_datapath
249255
ad_connect ${tx_phy}/tx_resetdone tx_resetdone
256+
ad_connect ${tx_phy}/gt_lcpllreset_in gt_lcpllreset
257+
ad_connect ${tx_phy}/gt_lcpllreset_done gt_lcpllresetdone
250258
}
251259
}
252260
}

‎projects/ad9081_fmca_ebz/vck190/system_bd.tcl‎

Lines changed: 0 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -16,10 +16,6 @@ source $ad_hdl_dir/projects/common/xilinx/dacfifo_bd.tcl
1616
set ADI_PHY_SEL 0
1717
set TRANSCEIVER_TYPE GTY
1818

19-
adi_project_files ad9081_fmca_ebz_vck190 [list \
20-
"$ad_hdl_dir/library/util_cdc/sync_bits.v" \
21-
]
22-
2319
source $ad_hdl_dir/projects/ad9081_fmca_ebz/common/ad9081_fmca_ebz_bd.tcl
2420
source $ad_hdl_dir/projects/scripts/adi_pd.tcl
2521

‎projects/ad9081_fmca_ebz/vck190/system_top.v‎

Lines changed: 12 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,6 @@
11
// ***************************************************************************
22
// ***************************************************************************
3-
// Copyright (C) 2021-2024 Analog Devices, Inc. All rights reserved.
3+
// Copyright (C) 2021-2025 Analog Devices, Inc. All rights reserved.
44
//
55
// In this HDL repository, there are many different and unique modules, consisting
66
// of various HDL (Verilog or VHDL) components. The individual modules are
@@ -126,14 +126,16 @@ module system_top #(
126126
wire [7:0] tx_data_p_loc;
127127
wire [7:0] tx_data_n_loc;
128128

129+
wire ref_clk;
129130
wire clkin6;
130131
wire clkin10;
131132
wire tx_device_clk;
132133
wire rx_device_clk;
133134
wire rx_sysref;
134135
wire tx_sysref;
135136

136-
wire gt_reset;
137+
wire mst_reset;
138+
wire gt_lcpll_reset;
137139
wire rx_reset_pll_and_datapath;
138140
wire tx_reset_pll_and_datapath;
139141
wire rx_reset_datapath;
@@ -143,8 +145,8 @@ module system_top #(
143145
wire tx_resetdone;
144146
wire tx_resetdone_s;
145147
wire gt_powergood;
146-
wire gt_reset_s;
147148
wire mst_resetdone;
149+
wire gt_lcpllresetdone;
148150

149151
// instantiations
150152
IBUFDS_GTE5 i_ibufds_ref_clk (
@@ -233,11 +235,13 @@ module system_top #(
233235
assign gpio_i[64] = rx_resetdone;
234236
assign gpio_i[65] = tx_resetdone;
235237
assign gpio_i[66] = mst_resetdone;
236-
assign gt_reset = gpio_o[67];
238+
assign gpio_i[67] = gt_lcpllresetdone;
237239
assign rx_reset_pll_and_datapath = gpio_o[68];
238240
assign tx_reset_pll_and_datapath = gpio_o[69];
239241
assign rx_reset_datapath = gpio_o[70];
240242
assign tx_reset_datapath = gpio_o[71];
243+
assign gt_lcpll_reset = gpio_o[72];
244+
assign mst_reset = gpio_o[73];
241245

242246
generate
243247
if (TX_NUM_LINKS > 1 & JESD_MODE == "8B10B") begin
@@ -276,11 +280,9 @@ module system_top #(
276280

277281
// Unused GPIOs
278282
assign gpio_i[59:57] = gpio_o[59:57];
279-
assign gpio_i[94:72] = gpio_o[94:72];
283+
assign gpio_i[94:74] = gpio_o[94:74];
280284
assign gpio_i[31:10] = gpio_o[31:10];
281285

282-
/* Reset should only be asserted if powergood is high */
283-
assign gt_reset_s = gt_reset & gt_powergood;
284286
assign mst_resetdone = rx_resetdone & tx_resetdone;
285287

286288
/* Hardwired to 1 if the RX/TX reset doesn't exit */
@@ -331,14 +333,16 @@ module system_top #(
331333
.tx_1_p (tx_data_p_loc[7:4]),
332334
.tx_1_n (tx_data_n_loc[7:4]),
333335

334-
.gt_reset (gt_reset_s),
336+
.gt_reset (mst_reset & gt_powergood),
337+
.gt_lcpllreset (gt_lcpll_reset),
335338
.gt_reset_rx_datapath (rx_reset_datapath),
336339
.gt_reset_tx_datapath (tx_reset_datapath),
337340
.gt_reset_rx_pll_and_datapath (rx_reset_pll_and_datapath),
338341
.gt_reset_tx_pll_and_datapath (tx_reset_pll_and_datapath),
339342
.gt_powergood (gt_powergood),
340343
.rx_resetdone (rx_resetdone_s),
341344
.tx_resetdone (tx_resetdone_s),
345+
.gt_lcpllresetdone (gt_lcpllresetdone),
342346

343347
.ref_clk_q0 (ref_clk),
344348
.ref_clk_q1 (ref_clk),

‎projects/ad9081_fmca_ebz/vpk180/system_bd.tcl‎

Lines changed: 0 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -16,10 +16,6 @@ source $ad_hdl_dir/projects/common/xilinx/dacfifo_bd.tcl
1616
set ADI_PHY_SEL 0
1717
set TRANSCEIVER_TYPE GTYP
1818

19-
adi_project_files ad9081_fmca_ebz_vpk180 [list \
20-
"$ad_hdl_dir/library/util_cdc/sync_bits.v" \
21-
]
22-
2319
source $ad_hdl_dir/projects/ad9081_fmca_ebz/common/ad9081_fmca_ebz_bd.tcl
2420
source $ad_hdl_dir/projects/scripts/adi_pd.tcl
2521

‎projects/ad9081_fmca_ebz/vpk180/system_top.v‎

Lines changed: 22 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -41,7 +41,8 @@ module system_top #(
4141
parameter RX_JESD_L = 4,
4242
parameter RX_NUM_LINKS = 1,
4343
parameter JESD_MODE = "8B10B",
44-
parameter GENERATE_LINK_CLK = 1
44+
parameter GENERATE_LINK_CLK = 1,
45+
parameter INTF_CFG = "RXTX"
4546
) (
4647

4748
input sys_clk_n,
@@ -153,23 +154,27 @@ module system_top #(
153154
wire [7:0] tx_data_p_loc;
154155
wire [7:0] tx_data_n_loc;
155156

157+
wire ref_clk;
156158
wire clkin6;
157159
wire clkin10;
158160
wire tx_device_clk;
159161
wire rx_device_clk;
160162
wire rx_sysref;
161163
wire tx_sysref;
162164

163-
wire gt_reset;
165+
wire mst_reset;
166+
wire gt_lcpll_reset;
164167
wire rx_reset_pll_and_datapath;
165168
wire tx_reset_pll_and_datapath;
166169
wire rx_reset_datapath;
167170
wire tx_reset_datapath;
168171
wire rx_resetdone;
172+
wire rx_resetdone_s;
169173
wire tx_resetdone;
174+
wire tx_resetdone_s;
170175
wire gt_powergood;
171-
wire gt_reset_s;
172176
wire mst_resetdone;
177+
wire gt_lcpllresetdone;
173178

174179
// instantiations
175180
IBUFDS_GTE5 i_ibufds_ref_clk (
@@ -259,11 +264,13 @@ module system_top #(
259264
assign gpio_i[64] = rx_resetdone;
260265
assign gpio_i[65] = tx_resetdone;
261266
assign gpio_i[66] = mst_resetdone;
262-
assign gt_reset = gpio_o[67];
267+
assign gpio_i[67] = gt_lcpllresetdone;
263268
assign rx_reset_pll_and_datapath = gpio_o[68];
264269
assign tx_reset_pll_and_datapath = gpio_o[69];
265270
assign rx_reset_datapath = gpio_o[70];
266271
assign tx_reset_datapath = gpio_o[71];
272+
assign gt_lcpll_reset = gpio_o[72];
273+
assign mst_reset = gpio_o[73];
267274

268275
generate
269276
if (TX_NUM_LINKS > 1 & JESD_MODE == "8B10B") begin
@@ -302,13 +309,15 @@ module system_top #(
302309

303310
// Unused GPIOs
304311
assign gpio_i[59:57] = gpio_o[59:57];
305-
assign gpio_i[94:72] = gpio_o[94:72];
312+
assign gpio_i[94:74] = gpio_o[94:74];
306313
assign gpio_i[31:10] = gpio_o[31:10];
307314

308-
/* Reset should only be asserted if powergood is high */
309-
assign gt_reset_s = gt_reset & gt_powergood;
310315
assign mst_resetdone = rx_resetdone & tx_resetdone;
311316

317+
/* Hardwired to 1 if the RX/TX reset doesn't exit */
318+
assign rx_resetdone = INTF_CFG != "TX" ? rx_resetdone_s : 1'b1;
319+
assign tx_resetdone = INTF_CFG != "RX" ? tx_resetdone_s : 1'b1;
320+
312321
system_wrapper i_system_wrapper (
313322
.gpio0_i (gpio_i[31:0]),
314323
.gpio0_o (gpio_o[31:0]),
@@ -380,17 +389,19 @@ module system_top #(
380389
.tx_1_p (tx_data_p_loc[7:4]),
381390
.tx_1_n (tx_data_n_loc[7:4]),
382391

383-
.gt_reset (gt_reset_s),
392+
.gt_reset (mst_reset & gt_powergood),
393+
.gt_lcpllreset (gt_lcpll_reset),
384394
.gt_reset_rx_datapath (rx_reset_datapath),
385395
.gt_reset_tx_datapath (tx_reset_datapath),
386396
.gt_reset_rx_pll_and_datapath (rx_reset_pll_and_datapath),
387397
.gt_reset_tx_pll_and_datapath (tx_reset_pll_and_datapath),
388398
.gt_powergood (gt_powergood),
389-
.rx_resetdone (rx_resetdone),
390-
.tx_resetdone (tx_resetdone),
399+
.rx_resetdone (rx_resetdone_s),
400+
.tx_resetdone (tx_resetdone_s),
401+
.gt_lcpllresetdone (gt_lcpllresetdone),
402+
391403
.ref_clk_q0 (ref_clk),
392404
.ref_clk_q1 (ref_clk),
393-
394405
.rx_device_clk (rx_device_clk),
395406
.tx_device_clk (tx_device_clk),
396407
.rx_sync_0 (rx_syncout),

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