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bluncanbluncan
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projects: ad9084_ebz: versal: Fix side swap
Because side B is connected to the first quad and side A on the second one, the Versal transceiver subsystem didn't allow us to swap them. Becaus we now support non-consecutive quads we can map them correctly. We can also support building side B use cases only for VCK190. Signed-off-by: Bogdan Luncan <[email protected]>
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-183
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8 files changed

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‎projects/ad9084_ebz/common/ad9084_ebz_bd.tcl‎

Lines changed: 55 additions & 42 deletions
Original file line numberDiff line numberDiff line change
@@ -22,13 +22,19 @@ if {$ASYMMETRIC_A_B_MODE} {
2222

2323
set HSCI_ENABLE [ expr { [info exists ad_project_params(HSCI_ENABLE)] \
2424
? $ad_project_params(HSCI_ENABLE) : 1 } ]
25+
set SIDE_B_ONLY [ expr { [info exists ad_project_params(SIDE_B_ONLY)] \
26+
? $ad_project_params(SIDE_B_ONLY) : 0 } ]
2527
set TDD_SUPPORT [ expr { [info exists ad_project_params(TDD_SUPPORT)] \
2628
? $ad_project_params(TDD_SUPPORT) : 0 } ]
2729
set SHARED_DEVCLK [ expr { [info exists ad_project_params(SHARED_DEVCLK)] \
2830
? $ad_project_params(SHARED_DEVCLK) : 0 } ]
2931
set DO_HAS_BYPASS [ expr { [info exists ad_project_params(DO_HAS_BYPASS)] \
3032
? $ad_project_params(DO_HAS_BYPASS) : 1 } ]
3133

34+
if {$SIDE_B_ONLY && $ASYMMETRIC_A_B_MODE} {
35+
error "ERROR: SIDE_B_ONLY and ASYMMETRIC_A_B_MODE cannot be both enabled!"
36+
}
37+
3238
if {$TDD_SUPPORT && !$SHARED_DEVCLK} {
3339
error "ERROR: Cannot enable TDD support without shared deviceclocks!"
3440
}
@@ -374,7 +380,7 @@ if {$ADI_PHY_SEL} {
374380

375381
set REF_CLK_RATE $ad_project_params(REF_CLK_RATE)
376382
# instantiate versal phy
377-
create_versal_jesd_xcvr_subsystem jesd204_phy $JESD_MODE $RX_NUM_OF_LANES $TX_NUM_OF_LANES $MAX_RX_LANE_RATE $MAX_TX_LANE_RATE $REF_CLK_RATE $TRANSCEIVER_TYPE RXTX
383+
create_versal_jesd_xcvr_subsystem jesd204_phy $JESD_MODE $RX_NUM_OF_LANES $TX_NUM_OF_LANES $MAX_RX_LANE_RATE $MAX_TX_LANE_RATE $REF_CLK_RATE $TRANSCEIVER_TYPE RXTX false
378384
# reset generator
379385
ad_ip_instance proc_sys_reset rx_device_clk_rstgen
380386
ad_connect rx_device_clk rx_device_clk_rstgen/slowest_sync_clk
@@ -744,50 +750,57 @@ if {$ADI_PHY_SEL} {
744750
}
745751

746752
# Export serial interfaces
747-
for {set j 0} {$j < $num_quads} {incr j} {
748-
if {$j < $num_quads_a} {
749-
create_bd_port -dir I -from 3 -to 0 rx_${j}_p
750-
create_bd_port -dir I -from 3 -to 0 rx_${j}_n
751-
create_bd_port -dir O -from 3 -to 0 tx_${j}_p
752-
create_bd_port -dir O -from 3 -to 0 tx_${j}_n
753-
ad_connect rx_${j}_p jesd204_phy/rx_${j}_p
754-
ad_connect rx_${j}_n jesd204_phy/rx_${j}_n
755-
ad_connect tx_${j}_p jesd204_phy/tx_${j}_p
756-
ad_connect tx_${j}_n jesd204_phy/tx_${j}_n
757-
} else {
758-
set jj [expr $j - $num_quads_a]
759-
create_bd_port -dir I -from 3 -to 0 rx_${j}_p
760-
create_bd_port -dir I -from 3 -to 0 rx_${j}_n
761-
create_bd_port -dir O -from 3 -to 0 tx_${j}_p
762-
create_bd_port -dir O -from 3 -to 0 tx_${j}_n
763-
ad_connect rx_${j}_p jesd204_phy_b/rx_${jj}_p
764-
ad_connect rx_${j}_n jesd204_phy_b/rx_${jj}_n
765-
ad_connect tx_${j}_p jesd204_phy_b/tx_${jj}_p
766-
ad_connect tx_${j}_n jesd204_phy_b/tx_${jj}_n
753+
if {!$SIDE_B_ONLY} {
754+
for {set j 0} {$j < $num_quads} {incr j} {
755+
if {$j < $num_quads_a} {
756+
create_bd_port -dir I -from 3 -to 0 rx_${j}_p
757+
create_bd_port -dir I -from 3 -to 0 rx_${j}_n
758+
create_bd_port -dir O -from 3 -to 0 tx_${j}_p
759+
create_bd_port -dir O -from 3 -to 0 tx_${j}_n
760+
ad_connect rx_${j}_p jesd204_phy/rx_${j}_p
761+
ad_connect rx_${j}_n jesd204_phy/rx_${j}_n
762+
ad_connect tx_${j}_p jesd204_phy/tx_${j}_p
763+
ad_connect tx_${j}_n jesd204_phy/tx_${j}_n
764+
} else {
765+
set jj [expr $j - $num_quads_a]
766+
create_bd_port -dir I -from 3 -to 0 rx_${j}_p
767+
create_bd_port -dir I -from 3 -to 0 rx_${j}_n
768+
create_bd_port -dir O -from 3 -to 0 tx_${j}_p
769+
create_bd_port -dir O -from 3 -to 0 tx_${j}_n
770+
ad_connect rx_${j}_p jesd204_phy_b/rx_${jj}_p
771+
ad_connect rx_${j}_n jesd204_phy_b/rx_${jj}_n
772+
ad_connect tx_${j}_p jesd204_phy_b/tx_${jj}_p
773+
ad_connect tx_${j}_n jesd204_phy_b/tx_${jj}_n
774+
}
767775
}
768-
}
769776

770-
if {$num_quads < $MAX_NUMBER_OF_QUADS} {
771-
# Create dummy ports for non-existing lanes
772-
for {set j $num_quads} {$j < $MAX_NUMBER_OF_QUADS} {incr j} {
773-
create_bd_port -dir I -from 3 -to 0 rx_${j}_p
774-
create_bd_port -dir I -from 3 -to 0 rx_${j}_n
775-
create_bd_port -dir O -from 3 -to 0 tx_${j}_p
776-
create_bd_port -dir O -from 3 -to 0 tx_${j}_n
777+
if {$num_quads < $MAX_NUMBER_OF_QUADS} {
778+
# Create dummy ports for non-existing lanes
779+
for {set j $num_quads} {$j < $MAX_NUMBER_OF_QUADS} {incr j} {
780+
create_bd_port -dir I -from 3 -to 0 rx_${j}_p
781+
create_bd_port -dir I -from 3 -to 0 rx_${j}_n
782+
create_bd_port -dir O -from 3 -to 0 tx_${j}_p
783+
create_bd_port -dir O -from 3 -to 0 tx_${j}_n
784+
}
785+
}
786+
} else {
787+
# Map the serial lanes to side B only
788+
for {set j 0} {$j < $num_quads} {incr j} {
789+
set idx [expr $j + 1]
790+
create_bd_port -dir I -from 3 -to 0 rx_${idx}_p
791+
create_bd_port -dir I -from 3 -to 0 rx_${idx}_n
792+
create_bd_port -dir O -from 3 -to 0 tx_${idx}_p
793+
create_bd_port -dir O -from 3 -to 0 tx_${idx}_n
794+
ad_connect rx_${idx}_p jesd204_phy/rx_${j}_p
795+
ad_connect rx_${idx}_n jesd204_phy/rx_${j}_n
796+
ad_connect tx_${idx}_p jesd204_phy/tx_${j}_p
797+
ad_connect tx_${idx}_n jesd204_phy/tx_${j}_n
777798
}
778-
# for {set j $num_quads_b} {$j < 1} {incr j} {
779-
# create_bd_port -dir I -from 3 -to 0 GT_Serial _${j}_0_grx_p
780-
# create_bd_port -dir I -from 3 -to 0 GT_Serial_${j}_0_grx_n
781-
# create_bd_port -dir O -from 3 -to 0 GT_Serial_${j}_0_gtx_p
782-
# create_bd_port -dir O -from 3 -to 0 GT_Serial_${j}_0_gtx_n
783-
# }
784-
785-
# for {set j $num_quads_a} {$j < 2} {incr j} {
786-
# create_bd_port -dir I -from 3 -to 0 GT_Serial_A_${j}_0_grx_p
787-
# create_bd_port -dir I -from 3 -to 0 GT_Serial_A_${j}_0_grx_n
788-
# create_bd_port -dir O -from 3 -to 0 GT_Serial_A_${j}_0_gtx_p
789-
# create_bd_port -dir O -from 3 -to 0 GT_Serial_A_${j}_0_gtx_n
790-
# }
799+
# Crete dummy ports for non-existing lanes
800+
create_bd_port -dir I -from 3 -to 0 rx_0_p
801+
create_bd_port -dir I -from 3 -to 0 rx_0_n
802+
create_bd_port -dir O -from 3 -to 0 tx_0_p
803+
create_bd_port -dir O -from 3 -to 0 tx_0_n
791804
}
792805
}
793806

‎projects/ad9084_ebz/vck190/system_bd.tcl‎

Lines changed: 13 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -18,10 +18,23 @@ if {$ASYMMETRIC_A_B_MODE == 1} {
1818
set dac_b_fifo_samples_per_converter [expr $ad_project_params(TX_B_KS_PER_CHANNEL)*1024]
1919
}
2020

21+
set SIDE_B_ONLY [ expr { [info exists ad_project_params(SIDE_B_ONLY)] \
22+
? $ad_project_params(SIDE_B_ONLY) : 0 } ]
23+
2124
source $ad_hdl_dir/projects/common/vck190/vck190_system_bd.tcl
2225
source $ad_hdl_dir/projects/common/xilinx/adcfifo_bd.tcl
2326
source $ad_hdl_dir/projects/common/xilinx/dacfifo_bd.tcl
2427

28+
if {!$SIDE_B_ONLY} {
29+
adi_project_files ad9084_ebz_vck190 [list \
30+
"system_top.v" \
31+
]
32+
} else {
33+
adi_project_files ad9084_ebz_vck190 [list \
34+
"system_top_side_b_only.v" \
35+
]
36+
}
37+
2538
set ADI_PHY_SEL 0
2639
set MAX_NUMBER_OF_QUADS 3
2740
set TRANSCEIVER_TYPE GTY

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