From 9bdea48bb8ceb2e342fd928d07284b0a8dfc60db Mon Sep 17 00:00:00 2001 From: Eren Terzioglu Date: Mon, 19 Jan 2026 10:53:11 +0100 Subject: [PATCH 1/6] arch/risc-v/espressif: Add AES accelerator support Add AES accelerator support for esp32[-c3|-c6|-h2|-p4] Signed-off-by: Eren Terzioglu --- arch/risc-v/src/common/espressif/Kconfig | 6 + arch/risc-v/src/common/espressif/Make.defs | 4 + arch/risc-v/src/common/espressif/esp_aes.c | 627 ++++++++++++++++++ arch/risc-v/src/common/espressif/esp_aes.h | 217 ++++++ arch/risc-v/src/common/espressif/esp_crypto.c | 52 ++ arch/risc-v/src/esp32c3/hal_esp32c3.mk | 1 + arch/risc-v/src/esp32c6/hal_esp32c6.mk | 1 + arch/risc-v/src/esp32h2/hal_esp32h2.mk | 1 + arch/risc-v/src/esp32p4/hal_esp32p4.mk | 1 + 9 files changed, 910 insertions(+) create mode 100644 arch/risc-v/src/common/espressif/esp_aes.c create mode 100644 arch/risc-v/src/common/espressif/esp_aes.h diff --git a/arch/risc-v/src/common/espressif/Kconfig b/arch/risc-v/src/common/espressif/Kconfig index dd181656eb411..41ceae53cd518 100644 --- a/arch/risc-v/src/common/espressif/Kconfig +++ b/arch/risc-v/src/common/espressif/Kconfig @@ -1023,6 +1023,12 @@ config ESPRESSIF_SHA_ACCELERATOR ---help--- Enable SHA accelerator support. +config ESPRESSIF_AES_ACCELERATOR + bool "AES Accelerator" + default n + ---help--- + Enable AES accelerator support. + config ESPRESSIF_ADC bool "Analog-to-digital converter (ADC)" default n diff --git a/arch/risc-v/src/common/espressif/Make.defs b/arch/risc-v/src/common/espressif/Make.defs index 2a7bdb6647c27..b21143f0b11d5 100644 --- a/arch/risc-v/src/common/espressif/Make.defs +++ b/arch/risc-v/src/common/espressif/Make.defs @@ -171,6 +171,10 @@ ifeq ($(CONFIG_ESPRESSIF_SHA_ACCELERATOR),y) CHIP_CSRCS += esp_sha.c endif +ifeq ($(CONFIG_ESPRESSIF_AES_ACCELERATOR),y) + CHIP_CSRCS += esp_aes.c +endif + ifeq ($(CONFIG_CRYPTO_CRYPTODEV_HARDWARE),y) CHIP_CSRCS += esp_crypto.c endif diff --git a/arch/risc-v/src/common/espressif/esp_aes.c b/arch/risc-v/src/common/espressif/esp_aes.c new file mode 100644 index 0000000000000..5e8eeadabd0a8 --- /dev/null +++ b/arch/risc-v/src/common/espressif/esp_aes.c @@ -0,0 +1,627 @@ +/**************************************************************************** + * arch/risc-v/src/common/espressif/esp_aes.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include +#include +#include +#include +#include + +#include +#include + +#include "riscv_internal.h" +#include "esp_aes.h" + +#include "esp_private/periph_ctrl.h" +#include "esp_private/esp_crypto_lock_internal.h" +#include "soc/periph_defs.h" +#include "hal/aes_hal.h" +#include "hal/aes_ll.h" +#include "soc/soc_caps.h" +#include "rom/cache.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define AES_BLK_SIZE (16) + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +static bool g_aes_inited; +static mutex_t g_aes_lock = NXMUTEX_INITIALIZER; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: aes_hw_setkey + * + * Description: + * Set AES hardware key and encryption/decryption mode + * + * Input Parameters: + * aes - AES object data pointer + * encrypt - True: encryption mode; False: decryption mode + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void aes_hw_setkey(struct esp_aes_s *aes, bool encrypt) +{ + aes_hal_setkey((uint8_t *)aes->key, aes->keybits / 8, encrypt); +} + +/**************************************************************************** + * Name: aes_hw_cypher + * + * Description: + * Process AES hardware encryption/decryption. + * + * Input Parameters: + * s - Input data pointer + * d - Output buffer pointer + * + * Returned Value: + * None. + * + ****************************************************************************/ + +static void aes_hw_cypher(const uint8_t *s, uint8_t *d) +{ + aes_hal_transform_block(s, d); +} + +/**************************************************************************** + * Name: gf128mul_x_ble + * + * Description: + * GF(2^128) multiplication function. + * + * Input Parameters: + * d - Result buffer + * s - Input data buffer + * + * Returned Value: + * None. + * + ****************************************************************************/ + +static void gf128mul_x_ble(uint8_t *d, const uint8_t *s) +{ + uint64_t a, b, ra, rb; + + memcpy(&a, s, 8); + memcpy(&b, s + 8, 8); + + ra = (a << 1) ^ (0x0087 >> (8 - ((b >> 63) << 3))); + rb = (a >> 63) | (b << 1); + + memcpy(d, &ra, 8); + memcpy(d + 8, &rb, 8); +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: esp_aes_ecb_cypher + * + * Description: + * Process AES ECB encryption/decryption. + * + * Input Parameters: + * aes - AES object data pointer + * encrypt - True: encryption mode; False: decryption mode + * input - Input data pointer + * output - Output buffer pointer + * size - Data size in bytes + * + * Returned Value: + * OK is returned on success. Otherwise, a negated errno value is returned. + * + ****************************************************************************/ + +int esp_aes_ecb_cypher(struct esp_aes_s *aes, bool encrypt, + const void *input, void *output, uint32_t size) +{ + int ret; + uint32_t i; + const uint8_t *s = (const uint8_t *)input; + uint8_t *d = (uint8_t *)output; + + DEBUGASSERT(aes && input && output); + DEBUGASSERT(size && ((size % AES_BLK_SIZE) == 0)); + + ret = nxmutex_lock(&g_aes_lock); + if (ret < 0) + { + return ret; + } + + aes_hw_setkey(aes, encrypt); + + for (i = 0; i < size; i += AES_BLK_SIZE) + { + aes_hw_cypher(s, d); + + s += AES_BLK_SIZE; + d += AES_BLK_SIZE; + } + + ret = nxmutex_unlock(&g_aes_lock); + if (ret < 0) + { + return ret; + } + + return OK; +} + +/**************************************************************************** + * Name: esp_aes_cbc_cypher + * + * Description: + * Process AES CBC encryption/decryption. + * + * Input Parameters: + * aes - AES object data pointer + * encrypt - True: encryption mode; False: decryption mode + * ivptr - Initialization vector pointer + * input - Input data pointer + * output - Output buffer pointer + * size - Data size in bytes + * + * Returned Value: + * OK is returned on success. Otherwise, a negated errno value is returned. + * + ****************************************************************************/ + +int esp_aes_cbc_cypher(struct esp_aes_s *aes, bool encrypt, + void *ivptr, const void *input, void *output, + uint32_t size) +{ + int ret; + uint32_t i; + uint32_t j; + const uint8_t *s = (const uint8_t *)input; + uint8_t *d = (uint8_t *)output; + uint8_t *iv = (uint8_t *)ivptr; + + DEBUGASSERT(aes && input && output && ivptr); + DEBUGASSERT(size && ((size % AES_BLK_SIZE) == 0)); + + ret = nxmutex_lock(&g_aes_lock); + if (ret < 0) + { + return ret; + } + + aes_hw_setkey(aes, encrypt); + + for (i = 0; i < size; i += AES_BLK_SIZE) + { + if (encrypt) + { + for (j = 0; j < AES_BLK_SIZE; j++) + { + d[j] = s[j] ^ iv[j]; + } + + aes_hw_cypher(d, d); + + memcpy(iv, d, AES_BLK_SIZE); + } + else + { + aes_hw_cypher(s, d); + + for (j = 0; j < AES_BLK_SIZE; j++) + { + d[j] = d[j] ^ iv[j]; + } + + memcpy(iv, s, AES_BLK_SIZE); + } + + s += AES_BLK_SIZE; + d += AES_BLK_SIZE; + } + + ret = nxmutex_unlock(&g_aes_lock); + if (ret < 0) + { + return ret; + } + + return OK; +} + +/**************************************************************************** + * Name: esp_aes_ctr_cypher + * + * Description: + * Process AES CTR encryption/decryption. + * + * Input Parameters: + * aes - AES object data pointer + * offptr - Offset buffer pointer + * cntptr - Counter buffer pointer + * cacheptr - Counter calculation buffer pointer + * input - Input data pointer + * output - Output buffer pointer + * size - Data size in bytes + * + * Returned Value: + * OK is returned on success. Otherwise, a negated errno value is returned. + * + ****************************************************************************/ + +int esp_aes_ctr_cypher(struct esp_aes_s *aes, uint32_t *offptr, + void *cntptr, void *cacheptr, const void *input, + void *output, uint32_t size) +{ + int ret; + uint32_t i; + uint32_t j; + uint32_t n; + uint8_t *cnt = (uint8_t *)cntptr; + uint8_t *cache = (uint8_t *)cacheptr; + const uint8_t *s = (const uint8_t *)input; + uint8_t *d = (uint8_t *)output; + + DEBUGASSERT(aes && offptr && cntptr && cacheptr && input && output); + DEBUGASSERT(size); + + ret = nxmutex_lock(&g_aes_lock); + if (ret < 0) + { + return ret; + } + + aes_hw_setkey(aes, true); + + n = *offptr; + for (i = 0; i < size; i++) + { + if (n == 0) + { + aes_hw_cypher(cnt, cache); + for (j = AES_BLK_SIZE - 1; j > 0; j--) + { + cnt[j]++; + if (cnt[j] != 0) + { + break; + } + } + } + + d[i] = s[i] ^ cache[n]; + + n = (n + 1) & (AES_BLK_SIZE - 1); + } + + *offptr = n; + + ret = nxmutex_unlock(&g_aes_lock); + if (ret < 0) + { + return ret; + } + + return OK; +} + +/**************************************************************************** + * Name: esp_aes_xts_cypher + * + * Description: + * Process AES XTS encryption/decryption. + * + * Input Parameters: + * aes - AES object data pointer + * encrypt - True: encryption mode; False: decryption mode + * unitptr - Unit data buffer pointer + * input - Input data pointer + * output - Output buffer pointer + * size - Data size in bytes + * + * Returned Value: + * OK is returned on success. Otherwise, a negated errno value is returned. + * + ****************************************************************************/ + +int esp_aes_xts_cypher(struct esp_aes_xts_s *aes, bool encrypt, + void *unitptr, const void *input, void *output, + uint32_t size) +{ + int ret; + uint32_t i; + uint32_t j; + uint32_t blks; + uint32_t rst; + uint8_t *t; + uint8_t *prev_output; + uint8_t tweak[AES_BLK_SIZE]; + uint8_t prev_tweak[AES_BLK_SIZE]; + uint8_t tmp[AES_BLK_SIZE]; + uint8_t *unit = (uint8_t *)unitptr; + const uint8_t *s = (const uint8_t *)input; + uint8_t *d = (uint8_t *)output; + + DEBUGASSERT(aes && unitptr && input && output); + + /* NIST SP 80-38E disallows data units larger than 2**20 blocks. */ + + DEBUGASSERT((size >= AES_BLK_SIZE) && + (size <= ((1 << 20) * AES_BLK_SIZE))); + + ret = nxmutex_lock(&g_aes_lock); + if (ret < 0) + { + return ret; + } + + blks = size / AES_BLK_SIZE; + rst = size % AES_BLK_SIZE; + + aes_hw_setkey(&aes->tweak, true); + aes_hw_cypher(unit, tweak); + + for (i = 0; i < blks; i++) + { + if (rst && (encrypt == false) && (blks == 1)) + { + memcpy(prev_tweak, tweak, AES_BLK_SIZE); + gf128mul_x_ble(tweak, tweak); + } + + for (j = 0; j < AES_BLK_SIZE; j++) + { + tmp[j] = s[j] ^ tweak[j]; + } + + aes_hw_setkey(&aes->crypt, encrypt); + aes_hw_cypher(tmp, tmp); + + for (j = 0; j < AES_BLK_SIZE; j++) + { + d[j] = tmp[j] ^ tweak[j]; + } + + gf128mul_x_ble(tweak, tweak); + + s += AES_BLK_SIZE; + d += AES_BLK_SIZE; + } + + if (rst) + { + t = encrypt ? tweak : prev_tweak; + prev_output = d - AES_BLK_SIZE; + + for (i = 0; i < rst; i++) + { + d[i] = prev_output[i]; + tmp[i] = s[i] ^ t[i]; + } + + for (; i < AES_BLK_SIZE; i++) + { + tmp[i] = prev_output[i] ^ t[i]; + } + + aes_hw_setkey(&aes->crypt, encrypt); + aes_hw_cypher(tmp, tmp); + + for (i = 0; i < AES_BLK_SIZE; i++) + { + prev_output[i] = tmp[i] ^ t[i]; + } + } + + ret = nxmutex_unlock(&g_aes_lock); + if (ret < 0) + { + return ret; + } + + return OK; +} + +/**************************************************************************** + * Name: esp_aes_setkey + * + * Description: + * Configure AES key. + * + * Input Parameters: + * aes - AES object data pointer + * keyptr - Key data pointer + * keybits - Key data bits + * + * Returned Value: + * OK is returned on success. Otherwise, a negated errno value is returned. + * + ****************************************************************************/ + +int esp_aes_setkey(struct esp_aes_s *aes, const void *keyptr, + uint16_t keybits) +{ + DEBUGASSERT(aes && keyptr); + + if ((keybits != 128) && (keybits != 256)) + { + return -EINVAL; + } + + aes->keybits = keybits; + memcpy(aes->key, keyptr, keybits / 8); + + return OK; +} + +/**************************************************************************** + * Name: esp_aes_xts_setkey + * + * Description: + * Configure AES XTS key. + * + * Input Parameters: + * aes - AES object data pointer + * keyptr - Key data pointer + * keybits - Key data bits + * + * Returned Value: + * OK is returned on success. Otherwise, a negated errno value is returned. + * + ****************************************************************************/ + +int esp_aes_xts_setkey(struct esp_aes_xts_s *aes, const void *keyptr, + uint16_t keybits) +{ + const uint8_t *key = (const uint8_t *)keyptr; + uint16_t half_keybits = keybits / 2; + + DEBUGASSERT(aes && keyptr); + + if ((keybits != 256) && (keybits != 512)) + { + return -EINVAL; + } + + aes->crypt.keybits = half_keybits; + memcpy(aes->crypt.key, key, half_keybits / 8); + + aes->tweak.keybits = half_keybits; + memcpy(aes->tweak.key, key + half_keybits / 8, half_keybits / 8); + + return OK; +} + +/**************************************************************************** + * Name: esp_aes_init + * + * Description: + * Initialize ESP device AES hardware. + * + * Input Parameters: + * None + * + * Returned Value: + * OK is returned on success. Otherwise, a negated errno value is returned. + * + ****************************************************************************/ + +int esp_aes_init(void) +{ + if (!g_aes_inited) + { + AES_RCC_ATOMIC() + { + aes_ll_enable_bus_clock(true); + aes_ll_reset_register(); + } + + g_aes_inited = true; + } + + return OK; +} + +#ifdef CONFIG_CRYPTO_AES + +int aes_cypher(void *out, const void *in, size_t size, + const void *iv, const void *key, size_t keysize, + int mode, int encrypt) +{ + int ret; + uint8_t iv_buf[AES_BLK_SIZE]; + uint8_t cache_buf[AES_BLK_SIZE]; + uint32_t nc_off; + struct esp_aes_s aes; + + if ((size & (AES_BLK_SIZE - 1)) != 0) + { + return -EINVAL; + } + + if (keysize != 16 && keysize != 32) + { + return -EINVAL; + } + + if ((mode != AES_MODE_ECB) && + (mode != AES_MODE_CBC) && + (mode != AES_MODE_CTR)) + { + return -EINVAL; + } + + ret = esp_aes_init(); + if (ret < 0) + { + return ret; + } + + ret = esp_aes_setkey(&aes, key, keysize * 8); + if (ret < 0) + { + return ret; + } + + switch (mode) + { + case AES_MODE_ECB: + ret = esp_aes_ecb_cypher(&aes, encrypt, in, out, size); + break; + case AES_MODE_CBC: + memcpy(iv_buf, iv, AES_BLK_SIZE); + ret = esp_aes_cbc_cypher(&aes, encrypt, iv_buf, in, out, size); + break; + case AES_MODE_CTR: + nc_off = 0; + memcpy(iv_buf, iv, AES_BLK_SIZE); + ret = esp_aes_ctr_cypher(&aes, &nc_off, iv_buf, cache_buf, + in, out, size); + break; + default: + ret = -EINVAL; + break; + } + + return ret; +} +#endif /* CONFIG_CRYPTO_AES */ diff --git a/arch/risc-v/src/common/espressif/esp_aes.h b/arch/risc-v/src/common/espressif/esp_aes.h new file mode 100644 index 0000000000000..d70675a0f6ee4 --- /dev/null +++ b/arch/risc-v/src/common/espressif/esp_aes.h @@ -0,0 +1,217 @@ +/**************************************************************************** + * arch/risc-v/src/common/espressif/esp_aes.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#ifndef __ARCH_RISCV_SRC_COMMON_ESPRESSIF_ESP_AES_H +#define __ARCH_RISCV_SRC_COMMON_ESPRESSIF_ESP_AES_H + +#include +#include + +#ifndef __ASSEMBLY__ + +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +/* AES private description */ + +struct esp_aes_s +{ + uint32_t key[8]; /* Key data value */ + uint16_t keybits; /* Key data bits */ +}; + +/* AES XTS private description */ + +struct esp_aes_xts_s +{ + struct esp_aes_s crypt; /* AES block encryption/decryption */ + struct esp_aes_s tweak; /* AES tweak encryption/decryption */ +}; + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Name: esp_aes_ecb_cypher + * + * Description: + * Process AES ECB encryption/decryption. + * + * Input Parameters: + * aes - AES object data pointer + * encrypt - True: encryption mode; False: decryption mode + * input - Input data pointer + * output - Output buffer pointer + * size - Data size in bytes + * + * Returned Value: + * OK is returned on success. Otherwise, a negated errno value is returned. + * + ****************************************************************************/ + +int esp_aes_ecb_cypher(struct esp_aes_s *aes, bool encrypt, + const void *input, void *output, uint32_t size); + +/**************************************************************************** + * Name: esp_aes_cbc_cypher + * + * Description: + * Process AES CBC encryption/decryption. + * + * Input Parameters: + * aes - AES object data pointer + * encrypt - True: encryption mode; False: decryption mode + * ivptr - Initialization vector pointer + * input - Input data pointer + * output - Output buffer pointer + * size - Data size in bytes + * + * Returned Value: + * OK is returned on success. Otherwise, a negated errno value is returned. + * + ****************************************************************************/ + +int esp_aes_cbc_cypher(struct esp_aes_s *aes, bool encrypt, + void *ivptr, const void *input, void *output, + uint32_t size); + +/**************************************************************************** + * Name: esp_aes_ctr_cypher + * + * Description: + * Process AES CTR encryption/decryption. + * + * Input Parameters: + * aes - AES object data pointer + * offptr - Offset buffer pointer + * cntptr - Counter buffer pointer + * cacheptr - Counter calculation buffer pointer + * input - Input data pointer + * output - Output buffer pointer + * size - Data size in bytes + * + * Returned Value: + * OK is returned on success. Otherwise, a negated errno value is returned. + * + ****************************************************************************/ + +int esp_aes_ctr_cypher(struct esp_aes_s *aes, uint32_t *offptr, + void *cntptr, void *cacheptr, const void *input, + void *output, uint32_t size); + +/**************************************************************************** + * Name: esp_aes_xts_cypher + * + * Description: + * Process AES XTS encryption/decryption. + * + * Input Parameters: + * aes - AES object data pointer + * encrypt - True: encryption mode; False: decryption mode + * unitptr - Unit data buffer pointer + * input - Input data pointer + * output - Output buffer pointer + * size - Data size in bytes + * + * Returned Value: + * OK is returned on success. Otherwise, a negated errno value is returned. + * + ****************************************************************************/ + +int esp_aes_xts_cypher(struct esp_aes_xts_s *aes, bool encrypt, + void *unitptr, const void *input, void *output, + uint32_t size); + +/**************************************************************************** + * Name: esp_aes_setkey + * + * Description: + * Configure AES key. + * + * Input Parameters: + * aes - AES object data pointer + * keyptr - Key data pointer + * keybits - Key data bits + * + * Returned Value: + * OK is returned on success. Otherwise, a negated errno value is returned. + * + ****************************************************************************/ + +int esp_aes_setkey(struct esp_aes_s *aes, const void *keyptr, + uint16_t keybits); + +/**************************************************************************** + * Name: esp_aes_xts_setkey + * + * Description: + * Configure AES XTS key. + * + * Input Parameters: + * aes - AES object data pointer + * keyptr - Key data pointer + * keybits - Key data bits + * + * Returned Value: + * OK is returned on success. Otherwise, a negated errno value is returned. + * + ****************************************************************************/ + +int esp_aes_xts_setkey(struct esp_aes_xts_s *aes, const void *keyptr, + uint16_t keybits); + +/**************************************************************************** + * Name: esp_aes_init + * + * Description: + * Initialize AES hardware driver. + * + * Input Parameters: + * None + * + * Returned Value: + * OK is returned on success. Otherwise, a negated errno value is returned. + * + ****************************************************************************/ + +int esp_aes_init(void); + +#ifdef __cplusplus +} +#endif +#undef EXTERN + +#endif /* __ASSEMBLY__ */ +#endif /* __ARCH_RISCV_SRC_COMMON_ESPRESSIF_ESP_AES_H */ diff --git a/arch/risc-v/src/common/espressif/esp_crypto.c b/arch/risc-v/src/common/espressif/esp_crypto.c index 976de492af7e2..6dec8339af6ec 100644 --- a/arch/risc-v/src/common/espressif/esp_crypto.c +++ b/arch/risc-v/src/common/espressif/esp_crypto.c @@ -34,6 +34,7 @@ #include #include "esp_sha.h" +#include "esp_aes.h" /**************************************************************************** * Private Functions Prototypes @@ -440,6 +441,23 @@ static int esp_newsession(uint32_t *sid, struct cryptoini *cri) switch (cri->cri_alg) { +#ifdef CONFIG_CRYPTO_AES + case CRYPTO_AES_CBC: + break; + + case CRYPTO_AES_CTR: + if ((cri->cri_klen / 8 - 4) != 16 && + (cri->cri_klen / 8 -4) != 32) + { + /* esp aes-ctr key bits just support 128 & 256 */ + + esp_freesession(i); + kmm_free(data); + return -EINVAL; + } + + break; +#endif case CRYPTO_SHA1: axf = &g_auth_hash_sha1_esp; goto sha_common; @@ -619,6 +637,7 @@ static int esp_process(struct cryptop *crp) struct cryptodesc *crd; struct esp_crypto_list *session; struct esp_crypto_data *data; + uint8_t iv[AESCTR_BLOCKSIZE]; uint32_t lid; int err = 0; @@ -645,6 +664,35 @@ static int esp_process(struct cryptop *crp) switch (data->alg) { +#ifdef CONFIG_CRYPTO_AES + case CRYPTO_AES_CBC: + err = aes_cypher(crp->crp_dst, crp->crp_buf, crd->crd_len, + crp->crp_iv, crd->crd_key, crd->crd_klen / 8, + AES_MODE_CBC, crd->crd_flags & CRD_F_ENCRYPT); + + if (err < 0) + { + return err; + } + break; + case CRYPTO_AES_CTR: + memcpy(iv, crd->crd_key + crd->crd_klen / 8 - AESCTR_NONCESIZE, + AESCTR_NONCESIZE); + memcpy(iv + AESCTR_NONCESIZE, crp->crp_iv, AESCTR_IVSIZE); + memcpy(iv + AESCTR_NONCESIZE + AESCTR_IVSIZE, + (uint8_t *)crp->crp_iv + AESCTR_IVSIZE, 4); + err = aes_cypher(crp->crp_dst, crp->crp_buf, crd->crd_len, iv, + crd->crd_key, + crd->crd_klen / 8 - AESCTR_NONCESIZE, + AES_MODE_CTR, crd->crd_flags & CRD_F_ENCRYPT); + + if (err < 0) + { + return err; + } + + break; +#endif case CRYPTO_SHA1: case CRYPTO_SHA2_256: if ((crp->crp_etype = hash(crp, crd, data, @@ -698,6 +746,10 @@ void hwcr_init(void) algs[CRYPTO_SHA2_256] = CRYPTO_ALG_FLAG_SUPPORTED; algs[CRYPTO_SHA1_HMAC] = CRYPTO_ALG_FLAG_SUPPORTED; algs[CRYPTO_SHA2_256_HMAC] = CRYPTO_ALG_FLAG_SUPPORTED; +#ifdef CONFIG_CRYPTO_AES + algs[CRYPTO_AES_CBC] = CRYPTO_ALG_FLAG_SUPPORTED; + algs[CRYPTO_AES_CTR] = CRYPTO_ALG_FLAG_SUPPORTED; +#endif esp_sha_init(); crypto_register(hwcr_id, algs, esp_newsession, diff --git a/arch/risc-v/src/esp32c3/hal_esp32c3.mk b/arch/risc-v/src/esp32c3/hal_esp32c3.mk index bf1a8d4555dc0..a5dd89601f536 100644 --- a/arch/risc-v/src/esp32c3/hal_esp32c3.mk +++ b/arch/risc-v/src/esp32c3/hal_esp32c3.mk @@ -244,6 +244,7 @@ CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_ CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_ana_conv$(DELIM)adc_oneshot_hal.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_pmu$(DELIM)brownout_hal.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_pmu$(DELIM)$(CHIP_SERIES)$(DELIM)rtc_cntl_hal.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_security$(DELIM)aes_hal.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_security$(DELIM)hmac_hal.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)cache_hal.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)efuse_hal.c diff --git a/arch/risc-v/src/esp32c6/hal_esp32c6.mk b/arch/risc-v/src/esp32c6/hal_esp32c6.mk index e7835860f51a1..fe0a60cbc5b8c 100644 --- a/arch/risc-v/src/esp32c6/hal_esp32c6.mk +++ b/arch/risc-v/src/esp32c6/hal_esp32c6.mk @@ -268,6 +268,7 @@ CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_ CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_system$(DELIM)port$(DELIM)soc$(DELIM)$(CHIP_SERIES)$(DELIM)system_internal.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_ana_conv$(DELIM)adc_hal_common.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_ana_conv$(DELIM)adc_oneshot_hal.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_security$(DELIM)aes_hal.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_security$(DELIM)apm_hal.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_security$(DELIM)hmac_hal.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_pmu$(DELIM)brownout_hal.c diff --git a/arch/risc-v/src/esp32h2/hal_esp32h2.mk b/arch/risc-v/src/esp32h2/hal_esp32h2.mk index ab23be666c130..d7763da5a9abe 100644 --- a/arch/risc-v/src/esp32h2/hal_esp32h2.mk +++ b/arch/risc-v/src/esp32h2/hal_esp32h2.mk @@ -251,6 +251,7 @@ CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_ CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_ana_conv$(DELIM)adc_oneshot_hal.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_security$(DELIM)apm_hal.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_pmu$(DELIM)brownout_hal.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_security$(DELIM)aes_hal.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_security$(DELIM)hmac_hal.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)cache_hal.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)efuse_hal.c diff --git a/arch/risc-v/src/esp32p4/hal_esp32p4.mk b/arch/risc-v/src/esp32p4/hal_esp32p4.mk index 3a8bbc5e4a05a..eeed96826228c 100644 --- a/arch/risc-v/src/esp32p4/hal_esp32p4.mk +++ b/arch/risc-v/src/esp32p4/hal_esp32p4.mk @@ -189,6 +189,7 @@ CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_ CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_ana_conv$(DELIM)$(CHIP_SERIES)$(DELIM)temperature_sensor_periph.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_ana_conv$(DELIM)adc_hal_common.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_ana_conv$(DELIM)adc_oneshot_hal.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_security$(DELIM)aes_hal.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_clock$(DELIM)$(CHIP_SERIES)$(DELIM)clk_tree_hal.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_dma$(DELIM)$(CHIP_SERIES)$(DELIM)gdma_periph.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_dma$(DELIM)gdma_hal_ahb_v2.c From e0473910ab3eed218cd85f8e55bb595bfac8e3ef Mon Sep 17 00:00:00 2001 From: Eren Terzioglu Date: Mon, 19 Jan 2026 12:05:18 +0100 Subject: [PATCH 2/6] boards/risc-v/espressif: Add AES accelerator board support Add AES accelerator board support for esp32[-c3|-c6|-h2|-p4] Signed-off-by: Eren Terzioglu --- .../esp32c3/esp32-c3-zero/src/esp32c3_bringup.c | 4 ++++ .../esp32c3-devkit/configs/crypto/defconfig | 4 ++-- .../esp32c3-devkit/src/esp32c3_bringup.c | 17 +++++++++++++++-- .../esp32c6-devkitc/configs/crypto/defconfig | 4 ++-- .../esp32c6-devkitc/src/esp32c6_bringup.c | 17 +++++++++++++++-- .../esp32h2-devkit/configs/crypto/defconfig | 4 ++-- .../esp32h2-devkit/src/esp32h2_bringup.c | 17 +++++++++++++++-- .../configs/crypto/defconfig | 9 +++++++-- 8 files changed, 62 insertions(+), 14 deletions(-) diff --git a/boards/risc-v/esp32c3/esp32-c3-zero/src/esp32c3_bringup.c b/boards/risc-v/esp32c3/esp32-c3-zero/src/esp32c3_bringup.c index a4f3f31086518..5d837e27c55ab 100644 --- a/boards/risc-v/esp32c3/esp32-c3-zero/src/esp32c3_bringup.c +++ b/boards/risc-v/esp32c3/esp32-c3-zero/src/esp32c3_bringup.c @@ -129,6 +129,10 @@ # include "espressif/esp_sha.h" #endif +#ifdef CONFIG_ESPRESSIF_AES_ACCELERATOR +# include "espressif/esp_aes.h" +#endif + #ifdef CONFIG_MMCSD_SPI # include "esp_board_mmcsd.h" #endif diff --git a/boards/risc-v/esp32c3/esp32c3-devkit/configs/crypto/defconfig b/boards/risc-v/esp32c3/esp32c3-devkit/configs/crypto/defconfig index 5ed4c25f2c08b..cf12dd424696e 100644 --- a/boards/risc-v/esp32c3/esp32c3-devkit/configs/crypto/defconfig +++ b/boards/risc-v/esp32c3/esp32c3-devkit/configs/crypto/defconfig @@ -8,8 +8,6 @@ # CONFIG_NSH_ARGCAT is not set # CONFIG_NSH_CMDOPT_HEXDUMP is not set # CONFIG_TESTING_CRYPTO_3DES_CBC is not set -# CONFIG_TESTING_CRYPTO_AES_CBC is not set -# CONFIG_TESTING_CRYPTO_AES_CTR is not set # CONFIG_TESTING_CRYPTO_AES_XTS is not set # CONFIG_TESTING_CRYPTO_HASH_HUGE_BLOCK is not set CONFIG_ALLOW_BSD_COMPONENTS=y @@ -29,9 +27,11 @@ CONFIG_BOARDCTL_RESET=y CONFIG_BOARD_LOOPSPERMSEC=15000 CONFIG_BUILTIN=y CONFIG_CRYPTO=y +CONFIG_CRYPTO_AES=y CONFIG_CRYPTO_CRYPTODEV=y CONFIG_CRYPTO_CRYPTODEV_HARDWARE=y CONFIG_CRYPTO_RANDOM_POOL=y +CONFIG_ESPRESSIF_AES_ACCELERATOR=y CONFIG_ESPRESSIF_SHA_ACCELERATOR=y CONFIG_FS_PROCFS=y CONFIG_IDLETHREAD_STACKSIZE=2048 diff --git a/boards/risc-v/esp32c3/esp32c3-devkit/src/esp32c3_bringup.c b/boards/risc-v/esp32c3/esp32c3-devkit/src/esp32c3_bringup.c index d586caab418ce..3d3a5fa09f845 100644 --- a/boards/risc-v/esp32c3/esp32c3-devkit/src/esp32c3_bringup.c +++ b/boards/risc-v/esp32c3/esp32c3-devkit/src/esp32c3_bringup.c @@ -124,6 +124,10 @@ # include "espressif/esp_sha.h" #endif +#ifdef CONFIG_ESPRESSIF_AES_ACCELERATOR +# include "espressif/esp_aes.h" +#endif + #ifdef CONFIG_MMCSD_SPI # include "esp_board_mmcsd.h" #endif @@ -191,14 +195,23 @@ int esp_bringup(void) } #endif -#if defined(CONFIG_ESPRESSIF_SHA_ACCELERATOR) && \ - !defined(CONFIG_CRYPTO_CRYPTODEV_HARDWARE) +#if !defined(CONFIG_CRYPTO_CRYPTODEV_HARDWARE) +# if defined(CONFIG_ESPRESSIF_SHA_ACCELERATOR) ret = esp_sha_init(); if (ret < 0) { syslog(LOG_ERR, "ERROR: Failed to initialize SHA: %d\n", ret); } +# endif + +# if defined(CONFIG_ESPRESSIF_AES_ACCELERATOR) + ret = esp_aes_init(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: Failed to initialize AES: %d\n", ret); + } +# endif #endif #ifdef CONFIG_ESPRESSIF_MWDT0 diff --git a/boards/risc-v/esp32c6/esp32c6-devkitc/configs/crypto/defconfig b/boards/risc-v/esp32c6/esp32c6-devkitc/configs/crypto/defconfig index c08d741ca036b..997c4b73f6739 100644 --- a/boards/risc-v/esp32c6/esp32c6-devkitc/configs/crypto/defconfig +++ b/boards/risc-v/esp32c6/esp32c6-devkitc/configs/crypto/defconfig @@ -8,8 +8,6 @@ # CONFIG_NSH_ARGCAT is not set # CONFIG_NSH_CMDOPT_HEXDUMP is not set # CONFIG_TESTING_CRYPTO_3DES_CBC is not set -# CONFIG_TESTING_CRYPTO_AES_CBC is not set -# CONFIG_TESTING_CRYPTO_AES_CTR is not set # CONFIG_TESTING_CRYPTO_AES_XTS is not set # CONFIG_TESTING_CRYPTO_HASH_HUGE_BLOCK is not set CONFIG_ALLOW_BSD_COMPONENTS=y @@ -30,9 +28,11 @@ CONFIG_BOARDCTL_RESET=y CONFIG_BOARD_LOOPSPERMSEC=15000 CONFIG_BUILTIN=y CONFIG_CRYPTO=y +CONFIG_CRYPTO_AES=y CONFIG_CRYPTO_CRYPTODEV=y CONFIG_CRYPTO_CRYPTODEV_HARDWARE=y CONFIG_CRYPTO_RANDOM_POOL=y +CONFIG_ESPRESSIF_AES_ACCELERATOR=y CONFIG_ESPRESSIF_SHA_ACCELERATOR=y CONFIG_FS_PROCFS=y CONFIG_IDLETHREAD_STACKSIZE=2048 diff --git a/boards/risc-v/esp32c6/esp32c6-devkitc/src/esp32c6_bringup.c b/boards/risc-v/esp32c6/esp32c6-devkitc/src/esp32c6_bringup.c index c5ef820693734..79e34a11ac7bd 100644 --- a/boards/risc-v/esp32c6/esp32c6-devkitc/src/esp32c6_bringup.c +++ b/boards/risc-v/esp32c6/esp32c6-devkitc/src/esp32c6_bringup.c @@ -131,6 +131,10 @@ # include "espressif/esp_sha.h" #endif +#ifdef CONFIG_ESPRESSIF_AES_ACCELERATOR +# include "espressif/esp_aes.h" +#endif + #ifdef CONFIG_NET_OA_TC6 # include "esp_board_oa_tc6.h" #endif @@ -209,14 +213,23 @@ int esp_bringup(void) } #endif -#if defined(CONFIG_ESPRESSIF_SHA_ACCELERATOR) && \ - !defined(CONFIG_CRYPTO_CRYPTODEV_HARDWARE) +#if !defined(CONFIG_CRYPTO_CRYPTODEV_HARDWARE) +# if defined(CONFIG_ESPRESSIF_SHA_ACCELERATOR) ret = esp_sha_init(); if (ret < 0) { syslog(LOG_ERR, "ERROR: Failed to initialize SHA: %d\n", ret); } +# endif + +# if defined(CONFIG_ESPRESSIF_AES_ACCELERATOR) + ret = esp_aes_init(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: Failed to initialize AES: %d\n", ret); + } +# endif #endif #ifdef CONFIG_ESPRESSIF_MWDT0 diff --git a/boards/risc-v/esp32h2/esp32h2-devkit/configs/crypto/defconfig b/boards/risc-v/esp32h2/esp32h2-devkit/configs/crypto/defconfig index 2aba6c7dc1e8e..0b41c4401f43d 100644 --- a/boards/risc-v/esp32h2/esp32h2-devkit/configs/crypto/defconfig +++ b/boards/risc-v/esp32h2/esp32h2-devkit/configs/crypto/defconfig @@ -8,8 +8,6 @@ # CONFIG_NSH_ARGCAT is not set # CONFIG_NSH_CMDOPT_HEXDUMP is not set # CONFIG_TESTING_CRYPTO_3DES_CBC is not set -# CONFIG_TESTING_CRYPTO_AES_CBC is not set -# CONFIG_TESTING_CRYPTO_AES_CTR is not set # CONFIG_TESTING_CRYPTO_AES_XTS is not set # CONFIG_TESTING_CRYPTO_HASH_HUGE_BLOCK is not set CONFIG_ALLOW_BSD_COMPONENTS=y @@ -29,9 +27,11 @@ CONFIG_BOARDCTL_RESET=y CONFIG_BOARD_LOOPSPERMSEC=15000 CONFIG_BUILTIN=y CONFIG_CRYPTO=y +CONFIG_CRYPTO_AES=y CONFIG_CRYPTO_CRYPTODEV=y CONFIG_CRYPTO_CRYPTODEV_HARDWARE=y CONFIG_CRYPTO_RANDOM_POOL=y +CONFIG_ESPRESSIF_AES_ACCELERATOR=y CONFIG_ESPRESSIF_SHA_ACCELERATOR=y CONFIG_FS_PROCFS=y CONFIG_IDLETHREAD_STACKSIZE=2048 diff --git a/boards/risc-v/esp32h2/esp32h2-devkit/src/esp32h2_bringup.c b/boards/risc-v/esp32h2/esp32h2-devkit/src/esp32h2_bringup.c index 8dae31d1fb461..efba1214cf8e4 100644 --- a/boards/risc-v/esp32h2/esp32h2-devkit/src/esp32h2_bringup.c +++ b/boards/risc-v/esp32h2/esp32h2-devkit/src/esp32h2_bringup.c @@ -121,6 +121,10 @@ # include "espressif/esp_sha.h" #endif +#ifdef CONFIG_ESPRESSIF_AES_ACCELERATOR +# include "espressif/esp_aes.h" +#endif + #ifdef CONFIG_MMCSD_SPI # include "esp_board_mmcsd.h" #endif @@ -188,14 +192,23 @@ int esp_bringup(void) } #endif -#if defined(CONFIG_ESPRESSIF_SHA_ACCELERATOR) && \ - !defined(CONFIG_CRYPTO_CRYPTODEV_HARDWARE) +#if !defined(CONFIG_CRYPTO_CRYPTODEV_HARDWARE) +# if defined(CONFIG_ESPRESSIF_SHA_ACCELERATOR) ret = esp_sha_init(); if (ret < 0) { syslog(LOG_ERR, "ERROR: Failed to initialize SHA: %d\n", ret); } +# endif + +# if defined(CONFIG_ESPRESSIF_AES_ACCELERATOR) + ret = esp_aes_init(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: Failed to initialize AES: %d\n", ret); + } +# endif #endif #ifdef CONFIG_ESPRESSIF_MWDT0 diff --git a/boards/risc-v/esp32p4/esp32p4-function-ev-board/configs/crypto/defconfig b/boards/risc-v/esp32p4/esp32p4-function-ev-board/configs/crypto/defconfig index 75fc237276727..9474a7a6c0d6e 100644 --- a/boards/risc-v/esp32p4/esp32p4-function-ev-board/configs/crypto/defconfig +++ b/boards/risc-v/esp32p4/esp32p4-function-ev-board/configs/crypto/defconfig @@ -8,9 +8,8 @@ # CONFIG_NSH_ARGCAT is not set # CONFIG_NSH_CMDOPT_HEXDUMP is not set # CONFIG_TESTING_CRYPTO_3DES_CBC is not set -# CONFIG_TESTING_CRYPTO_AES_CBC is not set -# CONFIG_TESTING_CRYPTO_AES_CTR is not set # CONFIG_TESTING_CRYPTO_AES_XTS is not set +# CONFIG_TESTING_CRYPTO_HASH_HUGE_BLOCK is not set CONFIG_ALLOW_BSD_COMPONENTS=y CONFIG_ARCH="risc-v" CONFIG_ARCH_BOARD="esp32p4-function-ev-board" @@ -27,9 +26,11 @@ CONFIG_BOARDCTL_RESET=y CONFIG_BOARD_LOOPSPERMSEC=15000 CONFIG_BUILTIN=y CONFIG_CRYPTO=y +CONFIG_CRYPTO_AES=y CONFIG_CRYPTO_CRYPTODEV=y CONFIG_CRYPTO_CRYPTODEV_HARDWARE=y CONFIG_CRYPTO_RANDOM_POOL=y +CONFIG_ESPRESSIF_AES_ACCELERATOR=y CONFIG_ESPRESSIF_SHA_ACCELERATOR=y CONFIG_EXPERIMENTAL=y CONFIG_FS_PROCFS=y @@ -54,6 +55,10 @@ CONFIG_START_YEAR=2019 CONFIG_SYSTEM_DUMPSTACK=y CONFIG_SYSTEM_NSH=y CONFIG_TESTING_CRYPTO=y +CONFIG_TESTING_CRYPTO_HASH=y +CONFIG_TESTING_CRYPTO_HASH_DISABLE_MD5=y +CONFIG_TESTING_CRYPTO_HASH_DISABLE_SHA512=y +CONFIG_TESTING_CRYPTO_STACKSIZE=4096 CONFIG_TESTING_GETPRIME=y CONFIG_TESTING_OSTEST=y CONFIG_UART0_SERIAL_CONSOLE=y From d52985b7020ea6643e300cbbf2e9a654a6b342e3 Mon Sep 17 00:00:00 2001 From: Eren Terzioglu Date: Mon, 19 Jan 2026 14:59:24 +0100 Subject: [PATCH 3/6] Docs/platforms/espressif: Add AES support docs Add AES support docs for esp32[-c3|-c6|-h2|-p4] Signed-off-by: Eren Terzioglu --- Documentation/platforms/risc-v/esp32c3/index.rst | 2 +- Documentation/platforms/risc-v/esp32c6/index.rst | 2 +- Documentation/platforms/risc-v/esp32h2/index.rst | 2 +- Documentation/platforms/risc-v/esp32p4/index.rst | 2 +- 4 files changed, 4 insertions(+), 4 deletions(-) diff --git a/Documentation/platforms/risc-v/esp32c3/index.rst b/Documentation/platforms/risc-v/esp32c3/index.rst index 4e6f911e63a74..24ac4e407f3b8 100644 --- a/Documentation/platforms/risc-v/esp32c3/index.rst +++ b/Documentation/platforms/risc-v/esp32c3/index.rst @@ -350,7 +350,7 @@ The following list indicates the state of peripherals' support in NuttX: Peripheral Support NOTES =========== ======= ==================== ADC Yes Oneshot -AES No +AES Yes Bluetooth Yes CAN/TWAI Yes DMA No diff --git a/Documentation/platforms/risc-v/esp32c6/index.rst b/Documentation/platforms/risc-v/esp32c6/index.rst index 04970c47cc994..7a58a99390f68 100644 --- a/Documentation/platforms/risc-v/esp32c6/index.rst +++ b/Documentation/platforms/risc-v/esp32c6/index.rst @@ -340,7 +340,7 @@ The following list indicates the state of peripherals' support in NuttX: Peripheral Support NOTES ============== ======= ==================== ADC Yes Oneshot and internal temperature sensor -AES No +AES Yes Bluetooth No CAN/TWAI Yes DMA Yes diff --git a/Documentation/platforms/risc-v/esp32h2/index.rst b/Documentation/platforms/risc-v/esp32h2/index.rst index 2cfecc9207c14..8b8936a441a3d 100644 --- a/Documentation/platforms/risc-v/esp32h2/index.rst +++ b/Documentation/platforms/risc-v/esp32h2/index.rst @@ -339,7 +339,7 @@ The following list indicates the state of peripherals' support in NuttX: Peripheral Support NOTES ============== ======= ==================== ADC Yes Oneshot and internal temperature sensor -AES No +AES Yes Bluetooth No CAN/TWAI Yes DMA Yes diff --git a/Documentation/platforms/risc-v/esp32p4/index.rst b/Documentation/platforms/risc-v/esp32p4/index.rst index f8bac1e7439e7..42d92d545276f 100644 --- a/Documentation/platforms/risc-v/esp32p4/index.rst +++ b/Documentation/platforms/risc-v/esp32p4/index.rst @@ -306,7 +306,7 @@ TRNG No ECDSA No TEE No APM No -AES No +AES Yes Digital Signature No Secure Boot No XTS_AES No From 626d9cc9756b2a685ba7e735e826f61a39894762 Mon Sep 17 00:00:00 2001 From: Eren Terzioglu Date: Wed, 21 Jan 2026 12:33:11 +0100 Subject: [PATCH 4/6] arch/xtensa/espressif: Add AES accelerator support Add AES accelerator support for esp32[-s2|-s3] Signed-off-by: Eren Terzioglu --- arch/xtensa/src/common/espressif/Kconfig | 7 + arch/xtensa/src/common/espressif/Make.defs | 7 + .../espressif/esp_aes.c} | 228 ++++++++---------- .../espressif/esp_aes.h} | 81 ++++--- arch/xtensa/src/common/espressif/esp_crypto.c | 51 ++++ arch/xtensa/src/esp32s2/hal.mk | 1 + arch/xtensa/src/esp32s3/Kconfig | 6 +- arch/xtensa/src/esp32s3/Make.defs | 4 - arch/xtensa/src/esp32s3/hal.mk | 1 + 9 files changed, 219 insertions(+), 167 deletions(-) rename arch/xtensa/src/{esp32s3/esp32s3_aes.c => common/espressif/esp_aes.c} (81%) rename arch/xtensa/src/{esp32s3/esp32s3_aes.h => common/espressif/esp_aes.h} (77%) diff --git a/arch/xtensa/src/common/espressif/Kconfig b/arch/xtensa/src/common/espressif/Kconfig index d2f1a0c41bbef..9e3171aee1284 100644 --- a/arch/xtensa/src/common/espressif/Kconfig +++ b/arch/xtensa/src/common/espressif/Kconfig @@ -115,6 +115,13 @@ config ESPRESSIF_SHA_ACCELERATOR ---help--- Enable SHA accelerator support. +config ESPRESSIF_AES_ACCELERATOR + bool "AES Accelerator" + depends on !ARCH_CHIP_ESP32 + default n + ---help--- + Enable AES accelerator support. + config ESPRESSIF_I2S bool default n diff --git a/arch/xtensa/src/common/espressif/Make.defs b/arch/xtensa/src/common/espressif/Make.defs index e254c8860f5ea..9c70fa621a43a 100644 --- a/arch/xtensa/src/common/espressif/Make.defs +++ b/arch/xtensa/src/common/espressif/Make.defs @@ -86,6 +86,13 @@ endif ifeq ($(CONFIG_ESPRESSIF_SHA_ACCELERATOR),y) CHIP_CSRCS += esp_sha.c +endif + +ifeq ($(CONFIG_ESPRESSIF_AES_ACCELERATOR),y) +CHIP_CSRCS += esp_aes.c +endif + +ifeq ($(CONFIG_ARCH_CHIP_ESP32),) ifeq ($(CONFIG_CRYPTO_CRYPTODEV_HARDWARE),y) CHIP_CSRCS += esp_crypto.c endif diff --git a/arch/xtensa/src/esp32s3/esp32s3_aes.c b/arch/xtensa/src/common/espressif/esp_aes.c similarity index 81% rename from arch/xtensa/src/esp32s3/esp32s3_aes.c rename to arch/xtensa/src/common/espressif/esp_aes.c index 85a4d954d2bd7..b4a4bf62d5114 100644 --- a/arch/xtensa/src/esp32s3/esp32s3_aes.c +++ b/arch/xtensa/src/common/espressif/esp_aes.c @@ -1,5 +1,7 @@ /**************************************************************************** - * arch/xtensa/src/esp32s3/esp32s3_aes.c + * arch/xtensa/src/common/espressif/esp_aes.c + * + * SPDX-License-Identifier: Apache-2.0 * * Licensed to the Apache Software Foundation (ASF) under one or more * contributor license agreements. See the NOTICE file distributed with @@ -32,11 +34,16 @@ #include #include -#include "xtensa.h" -#include "esp32s3_aes.h" +#include "chip.h" +#include "esp_aes.h" -#include "hardware/esp32s3_aes.h" -#include "hardware/esp32s3_system.h" +#include "esp_private/periph_ctrl.h" +#include "esp_private/esp_crypto_lock_internal.h" +#include "soc/periph_defs.h" +#include "hal/aes_hal.h" +#include "hal/aes_ll.h" +#include "soc/soc_caps.h" +#include "rom/cache.h" /**************************************************************************** * Pre-processor Definitions @@ -44,10 +51,6 @@ #define AES_BLK_SIZE (16) -#define AES_MODE_DECRYPT (BIT(2)) - -#define AES_IDLE_STATE (0) - /**************************************************************************** * Private Data ****************************************************************************/ @@ -74,19 +77,9 @@ static mutex_t g_aes_lock = NXMUTEX_INITIALIZER; * ****************************************************************************/ -static void aes_hw_setkey(struct esp32s3_aes_s *aes, bool encrypt) +static void aes_hw_setkey(struct esp_aes_s *aes, bool encrypt) { - int i; - uint32_t cryptbits = encrypt ? 0 : AES_MODE_DECRYPT; - uint32_t keybits = (aes->keybits / 64) - 2; - uint32_t keywords = aes->keybits / 32; - - putreg32(cryptbits | keybits, AES_MODE_REG); - - for (i = 0; i < keywords; ++i) - { - putreg32(aes->key[i], AES_KEY_0_REG + i * 4); - } + aes_hal_setkey((uint8_t *)aes->key, aes->keybits / 8, encrypt); } /**************************************************************************** @@ -106,27 +99,7 @@ static void aes_hw_setkey(struct esp32s3_aes_s *aes, bool encrypt) static void aes_hw_cypher(const uint8_t *s, uint8_t *d) { - uint32_t buffer[AES_BLK_SIZE / 4]; - - memcpy(buffer, s, AES_BLK_SIZE); - - putreg32(buffer[0], AES_TEXT_IN_0_REG + 0); - putreg32(buffer[1], AES_TEXT_IN_0_REG + 4); - putreg32(buffer[2], AES_TEXT_IN_0_REG + 8); - putreg32(buffer[3], AES_TEXT_IN_0_REG + 12); - - putreg32(AES_TRIGGER_M, AES_TRIGGER_REG); - - while (getreg32(AES_STATE_REG) != AES_IDLE_STATE) - { - } - - buffer[0] = getreg32(AES_TEXT_OUT_0_REG + 0); - buffer[1] = getreg32(AES_TEXT_OUT_0_REG + 4); - buffer[2] = getreg32(AES_TEXT_OUT_0_REG + 8); - buffer[3] = getreg32(AES_TEXT_OUT_0_REG + 12); - - memcpy(d, buffer, AES_BLK_SIZE); + aes_hal_transform_block(s, d); } /**************************************************************************** @@ -159,12 +132,11 @@ static void gf128mul_x_ble(uint8_t *d, const uint8_t *s) } #ifdef CONFIG_ESP32S3_AES_ACCELERATOR_TEST - /**************************************************************************** - * Name: esp32s3_aes_ecb_test + * Name: esp_aes_ecb_test * * Description: - * ESP32-S3 AES-ECB test. + * AES-ECB test for Espressif device. * * Input Parameters: * None @@ -174,14 +146,14 @@ static void gf128mul_x_ble(uint8_t *d, const uint8_t *s) * ****************************************************************************/ -static void esp32s3_aes_ecb_test(void) +static void esp_aes_ecb_test(void) { int ret; int i; int keybits; uint8_t encrypt_buf[16]; uint8_t decrypt_buf[16]; - struct esp32s3_aes_s aes; + struct esp_aes_s aes; const int size = 16; const uint32_t input[8] = @@ -215,10 +187,10 @@ static void esp32s3_aes_ecb_test(void) { keybits = i * 128 + 128; - ret = esp32s3_aes_setkey(&aes, key, keybits); + ret = esp_aes_setkey(&aes, key, keybits); DEBUGASSERT(ret == 0); - ret = esp32s3_aes_ecb_cypher(&aes, 1, input, encrypt_buf, size); + ret = esp_aes_ecb_cypher(&aes, 1, input, encrypt_buf, size); DEBUGASSERT(ret == 0); if (memcmp(encrypt_buf, result[i], size)) @@ -226,7 +198,7 @@ static void esp32s3_aes_ecb_test(void) DEBUGASSERT(0); } - ret = esp32s3_aes_ecb_cypher(&aes, 0, encrypt_buf, decrypt_buf, size); + ret = esp_aes_ecb_cypher(&aes, 0, encrypt_buf, decrypt_buf, size); DEBUGASSERT(ret == 0); if (memcmp(decrypt_buf, input, size)) @@ -239,10 +211,10 @@ static void esp32s3_aes_ecb_test(void) } /**************************************************************************** - * Name: esp32s3_aes_cbc_test + * Name: esp_aes_cbc_test * * Description: - * ESP32-S3 AES-CBC test. + * AES-CBC test for Espressif device. * * Input Parameters: * None @@ -252,7 +224,7 @@ static void esp32s3_aes_ecb_test(void) * ****************************************************************************/ -static void esp32s3_aes_cbc_test(void) +static void esp_aes_cbc_test(void) { int ret; int i; @@ -260,7 +232,7 @@ static void esp32s3_aes_cbc_test(void) uint8_t encrypt_buf[32]; uint8_t decrypt_buf[32]; uint8_t iv_buf[16]; - struct esp32s3_aes_s aes; + struct esp_aes_s aes; const int size = 32; const uint32_t input[8] = @@ -301,11 +273,11 @@ static void esp32s3_aes_cbc_test(void) { keybits = i * 128 + 128; - ret = esp32s3_aes_setkey(&aes, key, keybits); + ret = esp_aes_setkey(&aes, key, keybits); DEBUGASSERT(ret == 0); memcpy(iv_buf, iv, 16); - ret = esp32s3_aes_cbc_cypher(&aes, 1, iv_buf, input, + ret = esp_aes_cbc_cypher(&aes, 1, iv_buf, input, encrypt_buf, size); DEBUGASSERT(ret == 0); @@ -315,7 +287,7 @@ static void esp32s3_aes_cbc_test(void) } memcpy(iv_buf, iv, 16); - ret = esp32s3_aes_cbc_cypher(&aes, 0, iv_buf, encrypt_buf, + ret = esp_aes_cbc_cypher(&aes, 0, iv_buf, encrypt_buf, decrypt_buf, size); DEBUGASSERT(ret == 0); @@ -329,10 +301,10 @@ static void esp32s3_aes_cbc_test(void) } /**************************************************************************** - * Name: esp32s3_aes_ctr_test + * Name: esp_aes_ctr_test * * Description: - * ESP32-S3 AES-CTR test. + * AES-CTR test for Espressif device. * * Input Parameters: * None @@ -342,7 +314,7 @@ static void esp32s3_aes_cbc_test(void) * ****************************************************************************/ -static void esp32s3_aes_ctr_test(void) +static void esp_aes_ctr_test(void) { int ret; int i; @@ -352,7 +324,7 @@ static void esp32s3_aes_ctr_test(void) uint8_t cnt_buf[16]; uint8_t cache_buf[16]; uint32_t nc_off; - struct esp32s3_aes_s aes; + struct esp_aes_s aes; const int size = 32; const uint32_t input[8] = @@ -393,12 +365,12 @@ static void esp32s3_aes_ctr_test(void) { keybits = i * 128 + 128; - ret = esp32s3_aes_setkey(&aes, key, keybits); + ret = esp_aes_setkey(&aes, key, keybits); DEBUGASSERT(ret == 0); nc_off = 0; memcpy(cnt_buf, cnt, 16); - ret = esp32s3_aes_ctr_cypher(&aes, &nc_off, cnt_buf, cache_buf, + ret = esp_aes_ctr_cypher(&aes, &nc_off, cnt_buf, cache_buf, input, encrypt_buf, size); DEBUGASSERT(ret == 0); @@ -409,7 +381,7 @@ static void esp32s3_aes_ctr_test(void) nc_off = 0; memcpy(cnt_buf, cnt, 16); - ret = esp32s3_aes_ctr_cypher(&aes, &nc_off, cnt_buf, cache_buf, + ret = esp_aes_ctr_cypher(&aes, &nc_off, cnt_buf, cache_buf, encrypt_buf, decrypt_buf, size); DEBUGASSERT(ret == 0); @@ -423,10 +395,10 @@ static void esp32s3_aes_ctr_test(void) } /**************************************************************************** - * Name: esp32s3_aes_xts_test + * Name: esp_aes_xts_test * * Description: - * ESP32-S3 AES-XTS test. + * AES-XTS test for Espressif device. * * Input Parameters: * None @@ -436,7 +408,7 @@ static void esp32s3_aes_ctr_test(void) * ****************************************************************************/ -static void esp32s3_aes_xts_test(void) +static void esp_aes_xts_test(void) { int ret; int i; @@ -444,7 +416,7 @@ static void esp32s3_aes_xts_test(void) uint8_t encrypt_buf[32]; uint8_t decrypt_buf[32]; uint8_t unit_buf[16]; - struct esp32s3_aes_xts_s aes; + struct esp_aes_xts_s aes; int size; const uint32_t input[8] = @@ -504,7 +476,7 @@ static void esp32s3_aes_xts_test(void) { keybits = i * 256 + 256; - ret = esp32s3_aes_xts_setkey(&aes, key, keybits); + ret = esp_aes_xts_setkey(&aes, key, keybits); DEBUGASSERT(ret == 0); /* Encrypt/Decrypt 32 bytes */ @@ -512,7 +484,7 @@ static void esp32s3_aes_xts_test(void) size = 32; memcpy(unit_buf, unit, 16); - ret = esp32s3_aes_xts_cypher(&aes, true, unit_buf, input, + ret = esp_aes_xts_cypher(&aes, true, unit_buf, input, encrypt_buf, size); DEBUGASSERT(ret == 0); @@ -522,7 +494,7 @@ static void esp32s3_aes_xts_test(void) } memcpy(unit_buf, unit, 16); - ret = esp32s3_aes_xts_cypher(&aes, false, unit_buf, encrypt_buf, + ret = esp_aes_xts_cypher(&aes, false, unit_buf, encrypt_buf, decrypt_buf, size); DEBUGASSERT(ret == 0); @@ -536,7 +508,7 @@ static void esp32s3_aes_xts_test(void) size = 30; memcpy(unit_buf, unit, 16); - ret = esp32s3_aes_xts_cypher(&aes, true, unit_buf, input, + ret = esp_aes_xts_cypher(&aes, true, unit_buf, input, encrypt_buf, size); DEBUGASSERT(ret == 0); @@ -546,7 +518,7 @@ static void esp32s3_aes_xts_test(void) } memcpy(unit_buf, unit, 16); - ret = esp32s3_aes_xts_cypher(&aes, false, unit_buf, encrypt_buf, + ret = esp_aes_xts_cypher(&aes, false, unit_buf, encrypt_buf, decrypt_buf, size); DEBUGASSERT(ret == 0); @@ -559,14 +531,14 @@ static void esp32s3_aes_xts_test(void) } } -#endif +#endif /* CONFIG_ESP32S3_AES_ACCELERATOR_TEST */ /**************************************************************************** * Public Functions ****************************************************************************/ /**************************************************************************** - * Name: esp32s3_aes_ecb_cypher + * Name: esp_aes_ecb_cypher * * Description: * Process AES ECB encryption/decryption. @@ -583,8 +555,8 @@ static void esp32s3_aes_xts_test(void) * ****************************************************************************/ -int esp32s3_aes_ecb_cypher(struct esp32s3_aes_s *aes, bool encrypt, - const void *input, void *output, uint32_t size) +int esp_aes_ecb_cypher(struct esp_aes_s *aes, bool encrypt, + const void *input, void *output, uint32_t size) { int ret; uint32_t i; @@ -620,7 +592,7 @@ int esp32s3_aes_ecb_cypher(struct esp32s3_aes_s *aes, bool encrypt, } /**************************************************************************** - * Name: esp32s3_aes_cbc_cypher + * Name: esp_aes_cbc_cypher * * Description: * Process AES CBC encryption/decryption. @@ -638,9 +610,9 @@ int esp32s3_aes_ecb_cypher(struct esp32s3_aes_s *aes, bool encrypt, * ****************************************************************************/ -int esp32s3_aes_cbc_cypher(struct esp32s3_aes_s *aes, bool encrypt, - void *ivptr, const void *input, void *output, - uint32_t size) +int esp_aes_cbc_cypher(struct esp_aes_s *aes, bool encrypt, + void *ivptr, const void *input, void *output, + uint32_t size) { int ret; uint32_t i; @@ -699,7 +671,7 @@ int esp32s3_aes_cbc_cypher(struct esp32s3_aes_s *aes, bool encrypt, } /**************************************************************************** - * Name: esp32s3_aes_ctr_cypher + * Name: esp_aes_ctr_cypher * * Description: * Process AES CTR encryption/decryption. @@ -718,9 +690,9 @@ int esp32s3_aes_cbc_cypher(struct esp32s3_aes_s *aes, bool encrypt, * ****************************************************************************/ -int esp32s3_aes_ctr_cypher(struct esp32s3_aes_s *aes, uint32_t *offptr, - void *cntptr, void *cacheptr, const void *input, - void *output, uint32_t size) +int esp_aes_ctr_cypher(struct esp_aes_s *aes, uint32_t *offptr, + void *cntptr, void *cacheptr, const void *input, + void *output, uint32_t size) { int ret; uint32_t i; @@ -775,7 +747,7 @@ int esp32s3_aes_ctr_cypher(struct esp32s3_aes_s *aes, uint32_t *offptr, } /**************************************************************************** - * Name: esp32s3_aes_xts_cypher + * Name: esp_aes_xts_cypher * * Description: * Process AES XTS encryption/decryption. @@ -793,9 +765,9 @@ int esp32s3_aes_ctr_cypher(struct esp32s3_aes_s *aes, uint32_t *offptr, * ****************************************************************************/ -int esp32s3_aes_xts_cypher(struct esp32s3_aes_xts_s *aes, bool encrypt, - void *unitptr, const void *input, void *output, - uint32_t size) +int esp_aes_xts_cypher(struct esp_aes_xts_s *aes, bool encrypt, + void *unitptr, const void *input, void *output, + uint32_t size) { int ret; uint32_t i; @@ -892,7 +864,7 @@ int esp32s3_aes_xts_cypher(struct esp32s3_aes_xts_s *aes, bool encrypt, } /**************************************************************************** - * Name: esp32s3_aes_setkey + * Name: esp_aes_setkey * * Description: * Configure AES key. @@ -907,8 +879,8 @@ int esp32s3_aes_xts_cypher(struct esp32s3_aes_xts_s *aes, bool encrypt, * ****************************************************************************/ -int esp32s3_aes_setkey(struct esp32s3_aes_s *aes, const void *keyptr, - uint16_t keybits) +int esp_aes_setkey(struct esp_aes_s *aes, const void *keyptr, + uint16_t keybits) { DEBUGASSERT(aes && keyptr); @@ -924,7 +896,7 @@ int esp32s3_aes_setkey(struct esp32s3_aes_s *aes, const void *keyptr, } /**************************************************************************** - * Name: esp32s3_aes_xts_setkey + * Name: esp_aes_xts_setkey * * Description: * Configure AES XTS key. @@ -939,8 +911,8 @@ int esp32s3_aes_setkey(struct esp32s3_aes_s *aes, const void *keyptr, * ****************************************************************************/ -int esp32s3_aes_xts_setkey(struct esp32s3_aes_xts_s *aes, const void *keyptr, - uint16_t keybits) +int esp_aes_xts_setkey(struct esp_aes_xts_s *aes, const void *keyptr, + uint16_t keybits) { const uint8_t *key = (const uint8_t *)keyptr; uint16_t half_keybits = keybits / 2; @@ -962,10 +934,10 @@ int esp32s3_aes_xts_setkey(struct esp32s3_aes_xts_s *aes, const void *keyptr, } /**************************************************************************** - * Name: esp32s3_aes_init + * Name: esp_aes_init * * Description: - * Initialize ESP32-S3 AES hardware. + * Initialize ESP device AES hardware. * * Input Parameters: * None @@ -975,22 +947,22 @@ int esp32s3_aes_xts_setkey(struct esp32s3_aes_xts_s *aes, const void *keyptr, * ****************************************************************************/ -int esp32s3_aes_init(void) +int esp_aes_init(void) { - if (g_aes_inited == false) + if (!g_aes_inited) { - modifyreg32(SYSTEM_PERIP_CLK_EN1_REG, 0, SYSTEM_CRYPTO_AES_CLK_EN); - modifyreg32(SYSTEM_PERIP_RST_EN1_REG, SYSTEM_CRYPTO_AES_RST, 0); + AES_RCC_ATOMIC() + { + aes_ll_enable_bus_clock(true); + aes_ll_reset_register(); + } + g_aes_inited = true; } return OK; } -/**************************************************************************** - * Name: aes_cypher - ****************************************************************************/ - #ifdef CONFIG_CRYPTO_AES int aes_cypher(void *out, const void *in, size_t size, @@ -1001,18 +973,13 @@ int aes_cypher(void *out, const void *in, size_t size, uint8_t iv_buf[AES_BLK_SIZE]; uint8_t cache_buf[AES_BLK_SIZE]; uint32_t nc_off; - struct esp32s3_aes_s aes; + struct esp_aes_s aes; if ((size & (AES_BLK_SIZE - 1)) != 0) { return -EINVAL; } - if (mode == AES_MODE_CTR) - { - keysize -= 4; - } - if (keysize != 16 && keysize != 32) { return -EINVAL; @@ -1025,13 +992,13 @@ int aes_cypher(void *out, const void *in, size_t size, return -EINVAL; } - ret = esp32s3_aes_init(); + ret = esp_aes_init(); if (ret < 0) { return ret; } - ret = esp32s3_aes_setkey(&aes, key, keysize * 8); + ret = esp_aes_setkey(&aes, key, keysize * 8); if (ret < 0) { return ret; @@ -1040,17 +1007,17 @@ int aes_cypher(void *out, const void *in, size_t size, switch (mode) { case AES_MODE_ECB: - ret = esp32s3_aes_ecb_cypher(&aes, encrypt, in, out, size); + ret = esp_aes_ecb_cypher(&aes, encrypt, in, out, size); break; case AES_MODE_CBC: memcpy(iv_buf, iv, AES_BLK_SIZE); - ret = esp32s3_aes_cbc_cypher(&aes, encrypt, iv_buf, in, out, size); + ret = esp_aes_cbc_cypher(&aes, encrypt, iv_buf, in, out, size); break; case AES_MODE_CTR: nc_off = 0; memcpy(iv_buf, iv, AES_BLK_SIZE); - ret = esp32s3_aes_ctr_cypher(&aes, &nc_off, iv_buf, cache_buf, - in, out, size); + ret = esp_aes_ctr_cypher(&aes, &nc_off, iv_buf, cache_buf, + in, out, size); break; default: ret = -EINVAL; @@ -1059,22 +1026,31 @@ int aes_cypher(void *out, const void *in, size_t size, return ret; } - -#endif +#endif /* CONFIG_CRYPTO_AES */ #ifdef CONFIG_ESP32S3_AES_ACCELERATOR_TEST /**************************************************************************** - * Name: esp32s3_aes_test + * Name: esp_aes_test + * + * Description: + * Test AES implementation + * + * Input Parameters: + * None + * + * Returned Value: + * None + * ****************************************************************************/ -void esp32s3_aes_test(void) +void esp_aes_test(void) { - esp32s3_aes_ecb_test(); - esp32s3_aes_cbc_test(); - esp32s3_aes_ctr_test(); - esp32s3_aes_xts_test(); + esp_aes_ecb_test(); + esp_aes_cbc_test(); + esp_aes_ctr_test(); + esp_aes_xts_test(); syslog(LOG_INFO, "\nAES hardware accelerate test done.\n"); } -#endif +#endif /* CONFIG_ESP32S3_AES_ACCELERATOR_TEST */ diff --git a/arch/xtensa/src/esp32s3/esp32s3_aes.h b/arch/xtensa/src/common/espressif/esp_aes.h similarity index 77% rename from arch/xtensa/src/esp32s3/esp32s3_aes.h rename to arch/xtensa/src/common/espressif/esp_aes.h index 22d1f4fe3e771..2445c2481d6ab 100644 --- a/arch/xtensa/src/esp32s3/esp32s3_aes.h +++ b/arch/xtensa/src/common/espressif/esp_aes.h @@ -1,5 +1,5 @@ /**************************************************************************** - * arch/xtensa/src/esp32s3/esp32s3_aes.h + * arch/xtensa/src/common/espressif/esp_aes.h * * Licensed to the Apache Software Foundation (ASF) under one or more * contributor license agreements. See the NOTICE file distributed with @@ -22,8 +22,8 @@ * Included Files ****************************************************************************/ -#ifndef __ARCH_XTENSA_SRC_ESP32S3_ESP32S3_AES_H -#define __ARCH_XTENSA_SRC_ESP32S3_ESP32S3_AES_H +#ifndef __ARCH_XTENSA_SRC_COMMON_ESPRESSIF_ESP_AES_H +#define __ARCH_XTENSA_SRC_COMMON_ESPRESSIF_ESP_AES_H #include #include @@ -45,7 +45,7 @@ extern "C" /* AES private description */ -struct esp32s3_aes_s +struct esp_aes_s { uint32_t key[8]; /* Key data value */ uint16_t keybits; /* Key data bits */ @@ -53,10 +53,10 @@ struct esp32s3_aes_s /* AES XTS private description */ -struct esp32s3_aes_xts_s +struct esp_aes_xts_s { - struct esp32s3_aes_s crypt; /* AES block encryption/decryption */ - struct esp32s3_aes_s tweak; /* AES tweak encryption/decryption */ + struct esp_aes_s crypt; /* AES block encryption/decryption */ + struct esp_aes_s tweak; /* AES tweak encryption/decryption */ }; /**************************************************************************** @@ -64,7 +64,7 @@ struct esp32s3_aes_xts_s ****************************************************************************/ /**************************************************************************** - * Name: esp32s3_aes_ecb_cypher + * Name: esp_aes_ecb_cypher * * Description: * Process AES ECB encryption/decryption. @@ -81,11 +81,11 @@ struct esp32s3_aes_xts_s * ****************************************************************************/ -int esp32s3_aes_ecb_cypher(struct esp32s3_aes_s *aes, bool encrypt, - const void *input, void *output, uint32_t size); +int esp_aes_ecb_cypher(struct esp_aes_s *aes, bool encrypt, + const void *input, void *output, uint32_t size); /**************************************************************************** - * Name: esp32s3_aes_cbc_cypher + * Name: esp_aes_cbc_cypher * * Description: * Process AES CBC encryption/decryption. @@ -103,12 +103,12 @@ int esp32s3_aes_ecb_cypher(struct esp32s3_aes_s *aes, bool encrypt, * ****************************************************************************/ -int esp32s3_aes_cbc_cypher(struct esp32s3_aes_s *aes, bool encrypt, - void *ivptr, const void *input, void *output, - uint32_t size); +int esp_aes_cbc_cypher(struct esp_aes_s *aes, bool encrypt, + void *ivptr, const void *input, void *output, + uint32_t size); /**************************************************************************** - * Name: esp32s3_aes_ctr_cypher + * Name: esp_aes_ctr_cypher * * Description: * Process AES CTR encryption/decryption. @@ -127,12 +127,12 @@ int esp32s3_aes_cbc_cypher(struct esp32s3_aes_s *aes, bool encrypt, * ****************************************************************************/ -int esp32s3_aes_ctr_cypher(struct esp32s3_aes_s *aes, uint32_t *offptr, - void *cntptr, void *cacheptr, const void *input, - void *output, uint32_t size); +int esp_aes_ctr_cypher(struct esp_aes_s *aes, uint32_t *offptr, + void *cntptr, void *cacheptr, const void *input, + void *output, uint32_t size); /**************************************************************************** - * Name: esp32s3_aes_xts_cypher + * Name: esp_aes_xts_cypher * * Description: * Process AES XTS encryption/decryption. @@ -150,12 +150,12 @@ int esp32s3_aes_ctr_cypher(struct esp32s3_aes_s *aes, uint32_t *offptr, * ****************************************************************************/ -int esp32s3_aes_xts_cypher(struct esp32s3_aes_xts_s *aes, bool encrypt, - void *unitptr, const void *input, void *output, - uint32_t size); +int esp_aes_xts_cypher(struct esp_aes_xts_s *aes, bool encrypt, + void *unitptr, const void *input, void *output, + uint32_t size); /**************************************************************************** - * Name: esp32s3_aes_setkey + * Name: esp_aes_setkey * * Description: * Configure AES key. @@ -170,11 +170,11 @@ int esp32s3_aes_xts_cypher(struct esp32s3_aes_xts_s *aes, bool encrypt, * ****************************************************************************/ -int esp32s3_aes_setkey(struct esp32s3_aes_s *aes, const void *keyptr, - uint16_t keybits); +int esp_aes_setkey(struct esp_aes_s *aes, const void *keyptr, + uint16_t keybits); /**************************************************************************** - * Name: esp32s3_aes_xts_setkey + * Name: esp_aes_xts_setkey * * Description: * Configure AES XTS key. @@ -189,14 +189,14 @@ int esp32s3_aes_setkey(struct esp32s3_aes_s *aes, const void *keyptr, * ****************************************************************************/ -int esp32s3_aes_xts_setkey(struct esp32s3_aes_xts_s *aes, const void *keyptr, - uint16_t keybits); +int esp_aes_xts_setkey(struct esp_aes_xts_s *aes, const void *keyptr, + uint16_t keybits); /**************************************************************************** - * Name: esp32s3_aes_init + * Name: esp_aes_init * * Description: - * Initialize ESP32-S3 AES hardware driver. + * Initialize AES hardware driver. * * Input Parameters: * None @@ -206,17 +206,26 @@ int esp32s3_aes_xts_setkey(struct esp32s3_aes_xts_s *aes, const void *keyptr, * ****************************************************************************/ -int esp32s3_aes_init(void); +int esp_aes_init(void); #ifdef CONFIG_ESP32S3_AES_ACCELERATOR_TEST /**************************************************************************** - * Name: esp32s3_aes_test + * Name: esp_aes_test + * + * Description: + * Test AES implementation + * + * Input Parameters: + * None + * + * Returned Value: + * None + * ****************************************************************************/ -void esp32s3_aes_test(void); - -#endif +void esp_aes_test(void); +#endif /* CONFIG_ESP32S3_AES_ACCELERATOR_TEST */ #ifdef __cplusplus } @@ -224,4 +233,4 @@ void esp32s3_aes_test(void); #undef EXTERN #endif /* __ASSEMBLY__ */ -#endif /* __ARCH_RISCV_SRC_ESP32S3_LEGACY_ESP32S3_AES_H */ +#endif /* __ARCH_XTENSA_SRC_COMMON_ESPRESSIF_ESP_AES_H */ diff --git a/arch/xtensa/src/common/espressif/esp_crypto.c b/arch/xtensa/src/common/espressif/esp_crypto.c index 89830918fb969..4643ea654fb59 100644 --- a/arch/xtensa/src/common/espressif/esp_crypto.c +++ b/arch/xtensa/src/common/espressif/esp_crypto.c @@ -574,6 +574,23 @@ static int esp_newsession(uint32_t *sid, struct cryptoini *cri) switch (cri->cri_alg) { +#ifdef CONFIG_CRYPTO_AES + case CRYPTO_AES_CBC: + break; + + case CRYPTO_AES_CTR: + if ((cri->cri_klen / 8 - 4) != 16 && + (cri->cri_klen / 8 -4) != 32) + { + /* esp aes-ctr key bits just support 128 & 256 */ + + esp_freesession(i); + kmm_free(data); + return -EINVAL; + } + + break; +#endif case CRYPTO_SHA1: axf = &g_auth_hash_sha1_esp; goto sha_common; @@ -767,6 +784,7 @@ static int esp_process(struct cryptop *crp) struct cryptodesc *crd; struct esp_crypto_list *session; struct esp_crypto_data *data; + uint8_t iv[AESCTR_BLOCKSIZE]; uint32_t lid; int err = 0; @@ -793,6 +811,35 @@ static int esp_process(struct cryptop *crp) switch (data->alg) { +#ifdef CONFIG_CRYPTO_AES + case CRYPTO_AES_CBC: + err = aes_cypher(crp->crp_dst, crp->crp_buf, crd->crd_len, + crp->crp_iv, crd->crd_key, crd->crd_klen / 8, + AES_MODE_CBC, crd->crd_flags & CRD_F_ENCRYPT); + + if (err < 0) + { + return err; + } + break; + case CRYPTO_AES_CTR: + memcpy(iv, crd->crd_key + crd->crd_klen / 8 - AESCTR_NONCESIZE, + AESCTR_NONCESIZE); + memcpy(iv + AESCTR_NONCESIZE, crp->crp_iv, AESCTR_IVSIZE); + memcpy(iv + AESCTR_NONCESIZE + AESCTR_IVSIZE, + (uint8_t *)crp->crp_iv + AESCTR_IVSIZE, 4); + err = aes_cypher(crp->crp_dst, crp->crp_buf, crd->crd_len, iv, + crd->crd_key, + crd->crd_klen / 8 - AESCTR_NONCESIZE, + AES_MODE_CTR, crd->crd_flags & CRD_F_ENCRYPT); + + if (err < 0) + { + return err; + } + + break; +#endif case CRYPTO_SHA1: case CRYPTO_SHA2_256: case CRYPTO_SHA2_384: @@ -854,6 +901,10 @@ void hwcr_init(void) algs[CRYPTO_SHA2_256_HMAC] = CRYPTO_ALG_FLAG_SUPPORTED; algs[CRYPTO_SHA2_384_HMAC] = CRYPTO_ALG_FLAG_SUPPORTED; algs[CRYPTO_SHA2_512_HMAC] = CRYPTO_ALG_FLAG_SUPPORTED; +#ifdef CONFIG_CRYPTO_AES + algs[CRYPTO_AES_CBC] = CRYPTO_ALG_FLAG_SUPPORTED; + algs[CRYPTO_AES_CTR] = CRYPTO_ALG_FLAG_SUPPORTED; +#endif esp_sha_init(); crypto_register(hwcr_id, algs, esp_newsession, diff --git a/arch/xtensa/src/esp32s2/hal.mk b/arch/xtensa/src/esp32s2/hal.mk index d023f3f87e294..0018f3530b705 100644 --- a/arch/xtensa/src/esp32s2/hal.mk +++ b/arch/xtensa/src/esp32s2/hal.mk @@ -185,6 +185,7 @@ CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_ CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_timer$(DELIM)src$(DELIM)system_time.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)adc_hal_common.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)adc_oneshot_hal.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)aes_hal.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)$(CHIP_SERIES)$(DELIM)clk_tree_hal.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)$(CHIP_SERIES)$(DELIM)efuse_hal.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)wdt_hal_iram.c diff --git a/arch/xtensa/src/esp32s3/Kconfig b/arch/xtensa/src/esp32s3/Kconfig index edac2d873c798..3906fd80cb689 100644 --- a/arch/xtensa/src/esp32s3/Kconfig +++ b/arch/xtensa/src/esp32s3/Kconfig @@ -940,8 +940,12 @@ config ESP32S3_CAM Camera controller that receives parallel DVP data from image sensors. config ESP32S3_AES_ACCELERATOR - bool "AES Accelerator" + bool "AES Accelerator (legacy implementation: read help)" default n + select ESPRESSIF_AES_ACCELERATOR + ---help--- + This is a deprecated Kconfig macro. Its kept for retrocompatibility only. + Use "CONFIG_ESPRESSIF_AES_ACCELERATOR" instead. endmenu # ESP32-S3 Peripheral Selection diff --git a/arch/xtensa/src/esp32s3/Make.defs b/arch/xtensa/src/esp32s3/Make.defs index 6126987f6fabb..3e13b4a7925cc 100644 --- a/arch/xtensa/src/esp32s3/Make.defs +++ b/arch/xtensa/src/esp32s3/Make.defs @@ -181,10 +181,6 @@ ifeq ($(CONFIG_ESP32S3_SDMMC),y) CHIP_CSRCS += esp32s3_sdmmc.c endif -ifeq ($(CONFIG_ESP32S3_AES_ACCELERATOR),y) -CHIP_CSRCS += esp32s3_aes.c -endif - ifeq ($(CONFIG_ESP32S3_OPENETH),y) CHIP_CSRCS += esp_openeth.c endif diff --git a/arch/xtensa/src/esp32s3/hal.mk b/arch/xtensa/src/esp32s3/hal.mk index f728d2e4bd159..a2db0bd74d96c 100644 --- a/arch/xtensa/src/esp32s3/hal.mk +++ b/arch/xtensa/src/esp32s3/hal.mk @@ -169,6 +169,7 @@ CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_ CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_timer$(DELIM)src$(DELIM)esp_timer_init.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)adc_hal_common.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)adc_oneshot_hal.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)aes_hal.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)$(CHIP_SERIES)$(DELIM)clk_tree_hal.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)$(CHIP_SERIES)$(DELIM)efuse_hal.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)$(CHIP_SERIES)$(DELIM)rtc_cntl_hal.c From 0d426fed60465705b52ffbcd52d96bb4042290cd Mon Sep 17 00:00:00 2001 From: Eren Terzioglu Date: Wed, 21 Jan 2026 12:33:57 +0100 Subject: [PATCH 5/6] Docs/platforms/espressif: Add AES support docs Add AES support docs for esp32s2 Signed-off-by: Eren Terzioglu --- Documentation/platforms/xtensa/esp32s2/index.rst | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Documentation/platforms/xtensa/esp32s2/index.rst b/Documentation/platforms/xtensa/esp32s2/index.rst index ca1be4f5b0d82..1b34b84357744 100644 --- a/Documentation/platforms/xtensa/esp32s2/index.rst +++ b/Documentation/platforms/xtensa/esp32s2/index.rst @@ -376,7 +376,7 @@ The following list indicates the state of peripherals' support in NuttX: Peripheral Support NOTES ========== ======= ===== ADC Yes Oneshot -AES No +AES Yes CAN/TWAI Yes DAC No DMA Yes From a343c451f397c2c16e56a1ad3fa2a16b110bc0f3 Mon Sep 17 00:00:00 2001 From: Eren Terzioglu Date: Wed, 21 Jan 2026 12:34:55 +0100 Subject: [PATCH 6/6] boards/xtensa/espressif: Add AES accelerator board support Add AES accelerator board support for esp32[-s2|-s3] Signed-off-by: Eren Terzioglu --- .../esp32s2-saola-1/configs/crypto/defconfig | 4 +-- .../esp32s3-devkit/configs/crypto/defconfig | 4 +-- .../esp32s3-devkit/src/esp32s3_bringup.c | 27 ++++++++++++++----- .../esp32s3-korvo-2/src/esp32s3_bringup.c | 10 +++---- .../lckfb-szpi-esp32s3/src/esp32s3_bringup.c | 10 +++---- 5 files changed, 34 insertions(+), 21 deletions(-) diff --git a/boards/xtensa/esp32s2/esp32s2-saola-1/configs/crypto/defconfig b/boards/xtensa/esp32s2/esp32s2-saola-1/configs/crypto/defconfig index a40fa7c1430e7..4e89cb435d8be 100644 --- a/boards/xtensa/esp32s2/esp32s2-saola-1/configs/crypto/defconfig +++ b/boards/xtensa/esp32s2/esp32s2-saola-1/configs/crypto/defconfig @@ -9,8 +9,6 @@ # CONFIG_NSH_ARGCAT is not set # CONFIG_NSH_CMDOPT_HEXDUMP is not set # CONFIG_TESTING_CRYPTO_3DES_CBC is not set -# CONFIG_TESTING_CRYPTO_AES_CBC is not set -# CONFIG_TESTING_CRYPTO_AES_CTR is not set # CONFIG_TESTING_CRYPTO_AES_XTS is not set # CONFIG_TESTING_CRYPTO_HASH_HUGE_BLOCK is not set CONFIG_ALLOW_BSD_COMPONENTS=y @@ -26,10 +24,12 @@ CONFIG_ARCH_XTENSA=y CONFIG_BOARD_LOOPSPERMSEC=16717 CONFIG_BUILTIN=y CONFIG_CRYPTO=y +CONFIG_CRYPTO_AES=y CONFIG_CRYPTO_CRYPTODEV=y CONFIG_CRYPTO_CRYPTODEV_HARDWARE=y CONFIG_CRYPTO_RANDOM_POOL=y CONFIG_ESP32S2_UART0=y +CONFIG_ESPRESSIF_AES_ACCELERATOR=y CONFIG_ESPRESSIF_SHA_ACCELERATOR=y CONFIG_FS_PROCFS=y CONFIG_HAVE_CXX=y diff --git a/boards/xtensa/esp32s3/esp32s3-devkit/configs/crypto/defconfig b/boards/xtensa/esp32s3/esp32s3-devkit/configs/crypto/defconfig index bc7f243e53228..080d477a806cc 100644 --- a/boards/xtensa/esp32s3/esp32s3-devkit/configs/crypto/defconfig +++ b/boards/xtensa/esp32s3/esp32s3-devkit/configs/crypto/defconfig @@ -9,8 +9,6 @@ # CONFIG_NSH_ARGCAT is not set # CONFIG_NSH_CMDOPT_HEXDUMP is not set # CONFIG_TESTING_CRYPTO_3DES_CBC is not set -# CONFIG_TESTING_CRYPTO_AES_CBC is not set -# CONFIG_TESTING_CRYPTO_AES_CTR is not set # CONFIG_TESTING_CRYPTO_AES_XTS is not set # CONFIG_TESTING_CRYPTO_HASH_HUGE_BLOCK is not set CONFIG_ALLOW_BSD_COMPONENTS=y @@ -27,10 +25,12 @@ CONFIG_ARCH_XTENSA=y CONFIG_BOARD_LOOPSPERMSEC=16717 CONFIG_BUILTIN=y CONFIG_CRYPTO=y +CONFIG_CRYPTO_AES=y CONFIG_CRYPTO_CRYPTODEV=y CONFIG_CRYPTO_CRYPTODEV_HARDWARE=y CONFIG_CRYPTO_RANDOM_POOL=y CONFIG_ESP32S3_UART0=y +CONFIG_ESPRESSIF_AES_ACCELERATOR=y CONFIG_ESPRESSIF_SHA_ACCELERATOR=y CONFIG_FS_PROCFS=y CONFIG_HAVE_CXX=y diff --git a/boards/xtensa/esp32s3/esp32s3-devkit/src/esp32s3_bringup.c b/boards/xtensa/esp32s3/esp32s3-devkit/src/esp32s3_bringup.c index 3acd7db9887da..428cf70d29d5e 100644 --- a/boards/xtensa/esp32s3/esp32s3-devkit/src/esp32s3_bringup.c +++ b/boards/xtensa/esp32s3/esp32s3-devkit/src/esp32s3_bringup.c @@ -120,8 +120,8 @@ #include "esp32s3_board_sdmmc.h" #endif -#ifdef CONFIG_ESP32S3_AES_ACCELERATOR -# include "esp32s3_aes.h" +#ifdef CONFIG_ESPRESSIF_AES_ACCELERATOR +# include "espressif/esp_aes.h" #endif #ifdef CONFIG_ESPRESSIF_ADC @@ -149,6 +149,10 @@ # include "espressif/esp_sha.h" #endif +#ifdef CONFIG_ESPRESSIF_AES_ACCELERATOR +# include "espressif/esp_aes.h" +#endif + #ifdef CONFIG_ESPRESSIF_USE_ULP_RISCV_CORE # include "espressif/esp_ulp.h" # ifdef CONFIG_ESPRESSIF_ULP_USE_TEST_BIN @@ -247,14 +251,23 @@ int esp32s3_bringup(void) } #endif -#if defined(CONFIG_ESPRESSIF_SHA_ACCELERATOR) && \ - !defined(CONFIG_CRYPTO_CRYPTODEV_HARDWARE) +#if !defined(CONFIG_CRYPTO_CRYPTODEV_HARDWARE) +# if defined(CONFIG_ESPRESSIF_SHA_ACCELERATOR) ret = esp_sha_init(); if (ret < 0) { syslog(LOG_ERR, "ERROR: Failed to initialize SHA: %d\n", ret); } +# endif + +# if defined(CONFIG_ESPRESSIF_AES_ACCELERATOR) + ret = esp_aes_init(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: Failed to initialize AES: %d\n", ret); + } +# endif #endif #ifdef CONFIG_FS_PROCFS @@ -560,8 +573,8 @@ int esp32s3_bringup(void) } #endif -#ifdef CONFIG_ESP32S3_AES_ACCELERATOR - ret = esp32s3_aes_init(); +#ifdef CONFIG_ESPRESSIF_AES_ACCELERATOR + ret = esp_aes_init(); if (ret < 0) { syslog(LOG_ERR, "ERROR: Failed to initialize AES: %d\n", ret); @@ -569,7 +582,7 @@ int esp32s3_bringup(void) #ifdef CONFIG_ESP32S3_AES_ACCELERATOR_TEST else { - esp32s3_aes_test(); + esp_aes_test(); } #endif #endif diff --git a/boards/xtensa/esp32s3/esp32s3-korvo-2/src/esp32s3_bringup.c b/boards/xtensa/esp32s3/esp32s3-korvo-2/src/esp32s3_bringup.c index 775d9ba449660..a5f812feff3e8 100644 --- a/boards/xtensa/esp32s3/esp32s3-korvo-2/src/esp32s3_bringup.c +++ b/boards/xtensa/esp32s3/esp32s3-korvo-2/src/esp32s3_bringup.c @@ -110,8 +110,8 @@ #include "esp32s3_board_sdmmc.h" #endif -#ifdef CONFIG_ESP32S3_AES_ACCELERATOR -# include "esp32s3_aes.h" +#ifdef CONFIG_ESPRESSIF_AES_ACCELERATOR +# include "espressif/esp_aes.h" #endif #ifdef CONFIG_ESP32S3_ADC @@ -439,8 +439,8 @@ int esp32s3_bringup(void) } #endif -#ifdef CONFIG_ESP32S3_AES_ACCELERATOR - ret = esp32s3_aes_init(); +#ifdef CONFIG_ESPRESSIF_AES_ACCELERATOR + ret = esp_aes_init(); if (ret < 0) { syslog(LOG_ERR, "ERROR: Failed to initialize AES: %d\n", ret); @@ -448,7 +448,7 @@ int esp32s3_bringup(void) #ifdef CONFIG_ESP32S3_AES_ACCELERATOR_TEST else { - esp32s3_aes_test(); + esp_aes_test(); } #endif #endif diff --git a/boards/xtensa/esp32s3/lckfb-szpi-esp32s3/src/esp32s3_bringup.c b/boards/xtensa/esp32s3/lckfb-szpi-esp32s3/src/esp32s3_bringup.c index 8218a0ceae746..6051bc7e5a654 100644 --- a/boards/xtensa/esp32s3/lckfb-szpi-esp32s3/src/esp32s3_bringup.c +++ b/boards/xtensa/esp32s3/lckfb-szpi-esp32s3/src/esp32s3_bringup.c @@ -109,8 +109,8 @@ #include "esp32s3_board_sdmmc.h" #endif -#ifdef CONFIG_ESP32S3_AES_ACCELERATOR -# include "esp32s3_aes.h" +#ifdef CONFIG_ESPRESSIF_AES_ACCELERATOR +# include "espressif/esp_aes.h" #endif #ifdef CONFIG_SENSORS_QMI8658 @@ -468,8 +468,8 @@ int esp32s3_bringup(void) } #endif -#ifdef CONFIG_ESP32S3_AES_ACCELERATOR - ret = esp32s3_aes_init(); +#ifdef CONFIG_ESPRESSIF_AES_ACCELERATOR + ret = esp_aes_init(); if (ret < 0) { syslog(LOG_ERR, "ERROR: Failed to initialize AES: %d\n", ret); @@ -477,7 +477,7 @@ int esp32s3_bringup(void) #ifdef CONFIG_ESP32S3_AES_ACCELERATOR_TEST else { - esp32s3_aes_test(); + esp_aes_test(); } #endif #endif