From d0722186aff03f0c21b944ba4824a365ee861444 Mon Sep 17 00:00:00 2001 From: openhands Date: Fri, 17 Jul 2026 08:03:19 +0000 Subject: [PATCH 1/6] gd32f470vit6: fix flash pagesize and uClibc++ build errors - Add FMC_PROGMEM_PAGESIZE 4096 for CONFIG_GD32F4_FLASH_CONFIG_DEFAULT - Fix uClibc++ Make.defs workaround Co-authored-by: openhands --- arch/arm/src/gd32f4/gd32f4xx_progmem.c | 1 + libs/libxx/uClibc++/Make.defs | 4 ++-- 2 files changed, 3 insertions(+), 2 deletions(-) diff --git a/arch/arm/src/gd32f4/gd32f4xx_progmem.c b/arch/arm/src/gd32f4/gd32f4xx_progmem.c index e1ceed1767602..cd29b954016bc 100644 --- a/arch/arm/src/gd32f4/gd32f4xx_progmem.c +++ b/arch/arm/src/gd32f4/gd32f4xx_progmem.c @@ -47,6 +47,7 @@ # define FMC_PROGMEM_SECTOR_SIZES {_K(128), _K(128)} # define FMC_PROGMEM_SECTOR_NUM (2) +# define FMC_PROGMEM_PAGESIZE 4096 # define FMC_PROGMEM_SECTOR_SADDR (0x08040000) # define FMC_PROGMEM_SECTOR_EADDR (0x0807FFFF) diff --git a/libs/libxx/uClibc++/Make.defs b/libs/libxx/uClibc++/Make.defs index 1f13294a3f8d0..f28b59c04eb2f 100644 --- a/libs/libxx/uClibc++/Make.defs +++ b/libs/libxx/uClibc++/Make.defs @@ -31,8 +31,8 @@ uClibc++/uClibc++: uClibc++-$(UCLIBCXX_VERSION).tar.bz2 $(Q) tar -xf $< $(Q) $(DELFILE) $< $(Q) mv uClibc++-$(UCLIBCXX_VERSION) $@ - $(Q) patch -p0 < uClibc++/0001-uClibcxx-basic_definitions-fix-GCC-specific-definiti.patch -d uClibc++ - $(Q) patch -p0 < uClibc++/0001-uclibxx-use-overload-constructor-of-filebuf-ostream.patch -d uClibc++ + $(Q) patch -p1 < uClibc++/0001-uClibcxx-basic_definitions-fix-GCC-specific-definiti.patch -d uClibc++ + $(Q) patch -p1 < uClibc++/0001-uclibxx-use-overload-constructor-of-filebuf-ostream.patch -d uClibc++ endif $(TOPDIR)/include/uClibc++: uClibc++/uClibc++ From e432ff85b0cbd5c0a124436e76b96631fcaa84eb Mon Sep 17 00:00:00 2001 From: Jackson Qin Date: Mon, 20 Jul 2026 16:40:13 +0800 Subject: [PATCH 2/6] port gd32f470vit6 board support --- arch/arm/src/gd32f4/hardware/gd32f450_pinmap.h | 7 +++++-- boards/arm/gd32f4/drivers/Kconfig | 0 boards/arm/gd32f4/gd32f470vit6-eval | 1 + 3 files changed, 6 insertions(+), 2 deletions(-) create mode 100644 boards/arm/gd32f4/drivers/Kconfig create mode 120000 boards/arm/gd32f4/gd32f470vit6-eval diff --git a/arch/arm/src/gd32f4/hardware/gd32f450_pinmap.h b/arch/arm/src/gd32f4/hardware/gd32f450_pinmap.h index 53bfbeafebff3..8ec27228f5788 100644 --- a/arch/arm/src/gd32f4/hardware/gd32f450_pinmap.h +++ b/arch/arm/src/gd32f4/hardware/gd32f450_pinmap.h @@ -807,8 +807,11 @@ #define GPIO_UART3_TX_1 (GPIO_CFG_MODE_AF|GPIO_CFG_PUPD_PULLUP|GPIO_CFG_PP|GPIO_CFG_SPEED_50MHZ|GPIO_CFG_AF_8|GPIO_CFG_PORT_A|GPIO_CFG_PIN_0) #define GPIO_UART3_TX_2 (GPIO_CFG_MODE_AF|GPIO_CFG_PUPD_PULLUP|GPIO_CFG_PP|GPIO_CFG_SPEED_50MHZ|GPIO_CFG_AF_8|GPIO_CFG_PORT_C|GPIO_CFG_PIN_10) -#define GPIO_UART4_RX (GPIO_CFG_MODE_AF|GPIO_CFG_PUPD_PULLUP|GPIO_CFG_PP|GPIO_CFG_SPEED_50MHZ|GPIO_CFG_AF_8|GPIO_CFG_PORT_D|GPIO_CFG_PIN_2) -#define GPIO_UART4_TX (GPIO_CFG_MODE_AF|GPIO_CFG_PUPD_PULLUP|GPIO_CFG_PP|GPIO_CFG_SPEED_50MHZ|GPIO_CFG_AF_8|GPIO_CFG_PORT_C|GPIO_CFG_PIN_12) +#define GPIO_UART4_RX_1 (GPIO_CFG_MODE_AF|GPIO_CFG_PUPD_PULLUP|GPIO_CFG_PP|GPIO_CFG_SPEED_50MHZ|GPIO_CFG_AF_8|GPIO_CFG_PORT_D|GPIO_CFG_PIN_2) +#define GPIO_UART4_TX_1 (GPIO_CFG_MODE_AF|GPIO_CFG_PUPD_PULLUP|GPIO_CFG_PP|GPIO_CFG_SPEED_50MHZ|GPIO_CFG_AF_8|GPIO_CFG_PORT_C|GPIO_CFG_PIN_12) + +#define GPIO_UART4_RX_2 (GPIO_CFG_MODE_AF|GPIO_CFG_PUPD_PULLUP|GPIO_CFG_PP|GPIO_CFG_SPEED_50MHZ|GPIO_CFG_AF_11|GPIO_CFG_PORT_C|GPIO_CFG_PIN_11) +#define GPIO_UART4_TX_2 (GPIO_CFG_MODE_AF|GPIO_CFG_PUPD_PULLUP|GPIO_CFG_PP|GPIO_CFG_SPEED_50MHZ|GPIO_CFG_AF_11|GPIO_CFG_PORT_C|GPIO_CFG_PIN_10) #define GPIO_UART6_RX_1 (GPIO_CFG_MODE_AF|GPIO_CFG_PUPD_PULLUP|GPIO_CFG_PP|GPIO_CFG_SPEED_50MHZ|GPIO_CFG_AF_8|GPIO_CFG_PORT_E|GPIO_CFG_PIN_7) #define GPIO_UART6_RX_2 (GPIO_CFG_MODE_AF|GPIO_CFG_PUPD_PULLUP|GPIO_CFG_PP|GPIO_CFG_SPEED_50MHZ|GPIO_CFG_AF_8|GPIO_CFG_PORT_F|GPIO_CFG_PIN_6) diff --git a/boards/arm/gd32f4/drivers/Kconfig b/boards/arm/gd32f4/drivers/Kconfig new file mode 100644 index 0000000000000..e69de29bb2d1d diff --git a/boards/arm/gd32f4/gd32f470vit6-eval b/boards/arm/gd32f4/gd32f470vit6-eval new file mode 120000 index 0000000000000..be1271adc8974 --- /dev/null +++ b/boards/arm/gd32f4/gd32f470vit6-eval @@ -0,0 +1 @@ +/home/edy_jackson/workspace/project/nuttx_pro/nuttx_mcu/mcu_plat/platform/board_gd32f470vit6 \ No newline at end of file From 9788fb8d7234345b9b3248530d2cdb5031cc1244 Mon Sep 17 00:00:00 2001 From: Jackson Qin Date: Fri, 24 Jul 2026 18:58:11 +0800 Subject: [PATCH 3/6] gd32f4: add MCUboot application image and OTA partition Kconfig Enable GD32F4_APP_FORMAT_MCUBOOT and PROGMEM OTA slot options needed by the board mcuboot-loader/app configurations. Co-authored-by: Cursor --- arch/arm/src/gd32f4/Kconfig | 73 +++++++++++++++++++++++++++++++++++++ 1 file changed, 73 insertions(+) diff --git a/arch/arm/src/gd32f4/Kconfig b/arch/arm/src/gd32f4/Kconfig index c2d60e0c31122..43312cc39f502 100644 --- a/arch/arm/src/gd32f4/Kconfig +++ b/arch/arm/src/gd32f4/Kconfig @@ -192,6 +192,79 @@ config GD32F4_DFU Configure and position code for use with the GD MCU DFU bootloader. Do not select this option if you will load code using JTAG/SWM. +config GD32F4_HAVE_OTA_PARTITION + bool + default n + +choice + prompt "Application Image Format" + depends on ARCH_CHIP_GD32F4 + default GD32F4_APP_FORMAT_LEGACY + +config GD32F4_APP_FORMAT_LEGACY + bool "Legacy format" + +config GD32F4_APP_FORMAT_MCUBOOT + bool "MCUboot-bootable format" + select GD32F4_HAVE_OTA_PARTITION + depends on EXPERIMENTAL + +endchoice # Application Image Format + +if GD32F4_HAVE_OTA_PARTITION + +config GD32F4_MCUBOOT_HEADER_SIZE + hex "MCUboot image header size" + default 0x200 + depends on GD32F4_APP_FORMAT_MCUBOOT + +menuconfig GD32F4_PROGMEM_OTA_PARTITION + bool "MTD driver for OTA partition" + default n + depends on GD32F4_APP_FORMAT_MCUBOOT + select BCH + select MTD + select MTD_BYTE_WRITE + select MTD_PARTITION + select MTD_PROGMEM + select GD32F4_PROGMEM + +if GD32F4_PROGMEM_OTA_PARTITION + +config GD32F4_OTA_PRIMARY_SLOT_DEVPATH + string "Primary slot device path" + default "/dev/ota0" + +config GD32F4_OTA_SECONDARY_SLOT_DEVPATH + string "Secondary slot device path" + default "/dev/ota1" + +config GD32F4_OTA_SCRATCH_DEVPATH + string "Scratch partition device path" + default "/dev/otascratch" + +config GD32F4_OTA_PRIMARY_SLOT_OFFSET + hex "Primary slot offset" + default 0x20000 + +config GD32F4_OTA_SECONDARY_SLOT_OFFSET + hex "Secondary slot offset" + default 0x100000 + +config GD32F4_OTA_SCRATCH_OFFSET + hex "Scratch partition offset" + default 0x1e0000 + +config GD32F4_OTA_SLOT_SIZE + hex "Application image slot size (in bytes)" + default 0xe0000 + +config GD32F4_OTA_SCRATCH_SIZE + hex "Scratch partition size (in bytes)" + default 0x20000 + +endif # GD32F4_PROGMEM_OTA_PARTITION +endif # GD32F4_HAVE_OTA_PARTITION menu "GD32 Peripheral Support" From 113a0374998d573ea875dc3a57b0f4ef856c74b7 Mon Sep 17 00:00:00 2001 From: jacksonGreenStone <13117870426@163.com> Date: Sun, 26 Jul 2026 15:00:10 +0800 Subject: [PATCH 4/6] gd32f4: fix progmem OTA helpers and register gd32f470vit6-eval board. Point the out-of-tree board symlink at the sibling nuttx_mcu package path. --- arch/arm/src/gd32f4/gd32f4xx_progmem.c | 22 +++++++++++++++++----- boards/Kconfig | 19 ++++++++++++++++--- boards/arm/gd32f4/gd32f470vit6-eval | 2 +- 3 files changed, 34 insertions(+), 9 deletions(-) diff --git a/arch/arm/src/gd32f4/gd32f4xx_progmem.c b/arch/arm/src/gd32f4/gd32f4xx_progmem.c index cd29b954016bc..594edef413fb4 100644 --- a/arch/arm/src/gd32f4/gd32f4xx_progmem.c +++ b/arch/arm/src/gd32f4/gd32f4xx_progmem.c @@ -68,11 +68,23 @@ # define FMC_PROGMEM_SECTOR_EADDR (0x080FFFFF) # elif defined(CONFIG_GD32F4_FLASH_CONFIG_I) - -# define FMC_PROGMEM_SECTOR_SIZES {_K(16), _K(16), _K(16), _K(16)} -# define FMC_PROGMEM_SECTOR_NUM (4) -# define FMC_PROGMEM_SECTOR_SADDR (0x08100000) -# define FMC_PROGMEM_SECTOR_EADDR (0x0810FFFF) +# if defined(CONFIG_GD32F4_GD32F470) +/* GD32F470xI: 2048 KiB main flash @ 0x08000000, 4 KiB page erase. + * Expose full array so MCUboot OTA slots (loader/primary/secondary/scratch) + * can be partitioned via MTD progmem. + */ + +# define FMC_PROGMEM_SECTOR_SIZES {_K(256), _K(256), _K(256), _K(256)} +# define FMC_PROGMEM_SECTOR_NUM (512) +# define FMC_PROGMEM_SECTOR_SADDR (0x08000000) +# define FMC_PROGMEM_SECTOR_EADDR (0x081FFFFF) +# define FMC_PROGMEM_PAGESIZE 4096 +# else +# define FMC_PROGMEM_SECTOR_SIZES {_K(16), _K(16), _K(16), _K(16)} +# define FMC_PROGMEM_SECTOR_NUM (4) +# define FMC_PROGMEM_SECTOR_SADDR (0x08100000) +# define FMC_PROGMEM_SECTOR_EADDR (0x0810FFFF) +# endif # elif defined(CONFIG_GD32F4_FLASH_CONFIG_K) #if defined(CONFIG_GD32F4_GD32F450) diff --git a/boards/Kconfig b/boards/Kconfig index 5196f18cbc205..f3178ec02340d 100644 --- a/boards/Kconfig +++ b/boards/Kconfig @@ -559,9 +559,9 @@ config ARCH_BOARD_ESP32S3_BOX select ARCH_HAVE_IRQBUTTONS if ESPRESSIF_GPIO_IRQ ---help--- The ESP-BOX is an advanced AIoT, Edge AI, and IIoT applications development platform - released by Espressif Systems. The board is built on Espressif’s powerful ESP32-S3 + released by Espressif Systems. The board is built on Espressif¡¯s powerful ESP32-S3 Wi-Fi + Bluetooth 5 (LE) SoC and feature compact and beautiful enclosures. - Leveraging the multi-functional accessories and reliable examples from the repo’s, + Leveraging the multi-functional accessories and reliable examples from the repo¡¯s, these development boards cater to both prototyping new projects and building complex IoT systems, providing a perfect balance of form and function. @@ -845,6 +845,15 @@ config ARCH_BOARD_GD32F470IK_EVAL ---help--- GD32 MCU GD32F470IK-EVAL board based on the GD32F4 GD32F470IKT6 MCU. +config ARCH_BOARD_GD32F470VIT6_EVAL + bool "GD32 MCU GD32F470VIT6" + depends on ARCH_CHIP_GD32F470ZK + select ARCH_HAVE_LEDS + select ARCH_HAVE_BUTTONS + select ARCH_HAVE_IRQBUTTONS + ---help--- + GD32 MCU GD32F470VIT6-EVAL board based on the GD32F4 GD32F470VIT6 MCU. + config ARCH_BOARD_HIFIVE1_REVB bool "HiFive1 Rev B board" depends on ARCH_CHIP_FE310 @@ -3726,6 +3735,7 @@ config ARCH_BOARD default "gd32f470zk-eval" if ARCH_BOARD_GD32F470ZK_EVAL default "gd32f470zk-aiotbox" if ARCH_BOARD_GD32F470ZK_AIOTBOX default "gd32f470ik-eval" if ARCH_BOARD_GD32F470IK_EVAL + default "gd32f470vit6-eval" if ARCH_BOARD_GD32F470VIT6_EVAL default "hifive1-revb" if ARCH_BOARD_HIFIVE1_REVB default "hymini-stm32v" if ARCH_BOARD_HYMINI_STM32V default "imxrt1020-evk" if ARCH_BOARD_IMXRT1020_EVK @@ -4246,6 +4256,9 @@ endif if ARCH_BOARD_GD32F470IK_EVAL source "boards/arm/gd32f4/gd32f470ik-eval/Kconfig" endif +if ARCH_BOARD_GD32F470VIT6_EVAL +source "boards/arm/gd32f4/gd32f470vit6-eval/Kconfig" +endif if ARCH_BOARD_TEENSY_LC source "boards/arm/kl/teensy-lc/Kconfig" endif @@ -5555,7 +5568,7 @@ config BOARD_ETC_ROMFS_PASSWD_ENABLE The password is hashed at build time by the host tool tools/mkpasswd (compiled from tools/mkpasswd.c) using the Tiny - Encryption Algorithm (TEA) — the same algorithm used at runtime + Encryption Algorithm (TEA) ?? the same algorithm used at runtime in libs/libc/misc/lib_tea_encrypt.c. The plaintext password is never stored in the firmware image. diff --git a/boards/arm/gd32f4/gd32f470vit6-eval b/boards/arm/gd32f4/gd32f470vit6-eval index be1271adc8974..498fdee2cfad6 120000 --- a/boards/arm/gd32f4/gd32f470vit6-eval +++ b/boards/arm/gd32f4/gd32f470vit6-eval @@ -1 +1 @@ -/home/edy_jackson/workspace/project/nuttx_pro/nuttx_mcu/mcu_plat/platform/board_gd32f470vit6 \ No newline at end of file +../../../../nuttx_mcu/mcu_plat/platform/board_gd32f470vit6 \ No newline at end of file From 9729e8ab744f13e1d7b3bce4019a9675b4090afb Mon Sep 17 00:00:00 2001 From: jacksonGreenStone <13117870426@163.com> Date: Sun, 26 Jul 2026 16:27:21 +0800 Subject: [PATCH 5/6] syslog/rtt: enable CRLF conversion for Windows RTT viewers. The RTT syslog channel previously disabled CRLF, so LF-only lines staircased in MobaXterm. Leave sc_state default so CONFIG_SYSLOG_CRLF applies. --- drivers/syslog/syslog_channel.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/syslog/syslog_channel.c b/drivers/syslog/syslog_channel.c index 1abb3097fced5..6b9d7f5af8784 100644 --- a/drivers/syslog/syslog_channel.c +++ b/drivers/syslog/syslog_channel.c @@ -139,9 +139,9 @@ static syslog_channel_t g_rtt_channel = # ifdef CONFIG_SYSLOG_IOCTL , "rtt" # endif -# ifdef CONFIG_SYSLOG_CRLF - , SYSLOG_CHANNEL_DISABLE_CRLF -# endif + /* sc_state defaults to 0: CRLF conversion ON when CONFIG_SYSLOG_CRLF=y. + * Needed for MobaXterm / Windows RTT (LF-only causes staircase wrap). + */ }; #endif From c5aca3b77fbad06e383f8e8632058173a68e9482 Mon Sep 17 00:00:00 2001 From: jacksonGreenStone <13117870426@163.com> Date: Sun, 26 Jul 2026 23:06:45 +0800 Subject: [PATCH 6/6] gd32f4: add CAN0 driver and fix USART isconsole under RTT. Port bxCAN-style CAN0 support for Board1 and correct CONSOLE_UART ifdef handling so USART5 registers as /dev/ttyS3 when RTT is console. Co-authored-by: Cursor --- arch/arm/src/gd32f4/CMakeLists.txt | 4 + arch/arm/src/gd32f4/Kconfig | 42 +- arch/arm/src/gd32f4/Make.defs | 4 + arch/arm/src/gd32f4/gd32f4xx.h | 1 + arch/arm/src/gd32f4/gd32f4xx_can.c | 2546 +++++++++++++++++ arch/arm/src/gd32f4/gd32f4xx_can.h | 136 + arch/arm/src/gd32f4/gd32f4xx_serial.c | 20 +- .../src/gd32f4/hardware/gd32f450_memorymap.h | 4 +- arch/arm/src/gd32f4/hardware/gd32f4xx_can.h | 470 +++ 9 files changed, 3216 insertions(+), 11 deletions(-) create mode 100644 arch/arm/src/gd32f4/gd32f4xx_can.c create mode 100644 arch/arm/src/gd32f4/gd32f4xx_can.h create mode 100644 arch/arm/src/gd32f4/hardware/gd32f4xx_can.h diff --git a/arch/arm/src/gd32f4/CMakeLists.txt b/arch/arm/src/gd32f4/CMakeLists.txt index 674ecf5880ab8..a818d9a749020 100644 --- a/arch/arm/src/gd32f4/CMakeLists.txt +++ b/arch/arm/src/gd32f4/CMakeLists.txt @@ -66,4 +66,8 @@ if(CONFIG_GD32F4_SDIO) list(APPEND SRCS gd32f4xx_sdio.c) endif() +if(CONFIG_GD32F4_CAN) + list(APPEND SRCS gd32f4xx_can.c) +endif() + target_sources(arch PRIVATE ${SRCS}) diff --git a/arch/arm/src/gd32f4/Kconfig b/arch/arm/src/gd32f4/Kconfig index 43312cc39f502..fb2d6f1110744 100644 --- a/arch/arm/src/gd32f4/Kconfig +++ b/arch/arm/src/gd32f4/Kconfig @@ -343,12 +343,14 @@ config GD32F4_BKPSRAM config GD32F4_CAN0 bool "CAN0" select CAN + select ARCH_HAVE_CAN_ERRORS select GD32F4_CAN default n config GD32F4_CAN1 bool "CAN1" select CAN + select ARCH_HAVE_CAN_ERRORS select GD32F4_CAN default n @@ -1893,7 +1895,7 @@ config USART5_RS485_DIR_POLARITY int "Configure USART5 RS-485 DIR pin polarity" default 1 range 0 1 - depends on USART1_RS485 + depends on USART5_RS485 ---help--- Polarity of GPIO_USART5_RS485_DIR pin for RS-485 on USART5. The state on DIR pin: 0 - receive , 1 - transmit. @@ -2655,6 +2657,44 @@ config GD32F4_USB_ITRMP menu "CAN driver configuration" depends on GD32F4_CAN +config GD32F4_CAN0_BAUD + int "CAN0 BAUD" + depends on GD32F4_CAN0 + default 500000 + ---help--- + CAN0 BAUD rate. Required if CONFIG_GD32F4_CAN0 is defined. + Default 500000 for Board1 Power CAN MVP. + +config GD32F4_CAN1_BAUD + int "CAN1 BAUD" + depends on GD32F4_CAN1 + default 500000 + ---help--- + CAN1 BAUD rate. Required if CONFIG_GD32F4_CAN1 is defined. + +config GD32F4_CAN_TSEG1 + int "TSEG1 quanta" + default 6 + ---help--- + The number of CAN time quanta in segment 1. Default: 6 + (bit time = TSEG1 + TSEG2 + 1 = 14 quanta with default TSEG2). + +config GD32F4_CAN_TSEG2 + int "TSEG2 quanta" + default 7 + ---help--- + The number of CAN time quanta in segment 2. Default: 7 + +config GD32F4_CAN_REGDEBUG + bool "CAN Register level debug" + depends on DEBUG_CAN_INFO + default n + ---help--- + Output detailed register-level CAN device debug information. + Requires also CONFIG_DEBUG_CAN_INFO. + +comment "Loopback mode uses Device Drivers -> CAN Driver Support -> CONFIG_CAN_LOOPBACK" + endmenu # "CAN driver configuration" diff --git a/arch/arm/src/gd32f4/Make.defs b/arch/arm/src/gd32f4/Make.defs index 989cee6c94f56..f1be4e8b6623d 100644 --- a/arch/arm/src/gd32f4/Make.defs +++ b/arch/arm/src/gd32f4/Make.defs @@ -64,3 +64,7 @@ endif ifeq ($(CONFIG_GD32F4_SDIO),y) CHIP_CSRCS += gd32f4xx_sdio.c endif + +ifeq ($(CONFIG_GD32F4_CAN),y) +CHIP_CSRCS += gd32f4xx_can.c +endif diff --git a/arch/arm/src/gd32f4/gd32f4xx.h b/arch/arm/src/gd32f4/gd32f4xx.h index fb743e82d555c..9b2a0c3015869 100644 --- a/arch/arm/src/gd32f4/gd32f4xx.h +++ b/arch/arm/src/gd32f4/gd32f4xx.h @@ -50,5 +50,6 @@ #include "gd32f4xx_i2c.h" #include "gd32f4xx_syscfg.h" #include "gd32f4xx_sdio.h" +#include "gd32f4xx_can.h" #endif /* __ARCH_ARM_SRC_GD32F4_GD32F4XX_H */ diff --git a/arch/arm/src/gd32f4/gd32f4xx_can.c b/arch/arm/src/gd32f4/gd32f4xx_can.c new file mode 100644 index 0000000000000..a134800341bfc --- /dev/null +++ b/arch/arm/src/gd32f4/gd32f4xx_can.c @@ -0,0 +1,2546 @@ +/**************************************************************************** + * arch/arm/src/gd32f4/gd32f4xx_can.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +#include "arm_internal.h" +#include "chip.h" +#include "gd32f4xx.h" +#include "gd32f4xx_rcu.h" +#include "gd32f4xx_can.h" +#include "gd32f4xx_gpio.h" + +#if defined(CONFIG_CAN) && \ + (defined(CONFIG_GD32F4_CAN0) || defined(CONFIG_GD32F4_CAN1)) + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Delays *******************************************************************/ + +/* Time out for INAK bit */ + +#define INAK_TIMEOUT 65535 + +/* Bit timing ***************************************************************/ + +#define CAN_BIT_QUANTA (CONFIG_GD32F4_CAN_TSEG1 + CONFIG_GD32F4_CAN_TSEG2 + 1) + +#ifndef CONFIG_DEBUG_CAN_INFO +# undef CONFIG_GD32F4_CAN_REGDEBUG +#endif + +/* CAN error interrupts */ + +#ifdef CONFIG_CAN_ERRORS +# define GD32_CAN_ERRINT (CAN_IER_LECIE | CAN_IER_ERRIE | \ + CAN_IER_BOFIE | CAN_IER_EPVIE | \ + CAN_IER_EWGIE) +#endif + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +struct gd32_can_s +{ + uint8_t port; /* CAN port number (1 or 2) */ + uint8_t canrx[2]; /* CAN RX FIFO 0/1 IRQ number */ + uint8_t cantx; /* CAN TX IRQ number */ +#ifdef CONFIG_CAN_ERRORS + uint8_t cansce; /* CAN SCE IRQ number */ +#endif + uint8_t filter; /* Filter number */ + uint32_t base; /* Base address of the CAN control registers */ + uint32_t fbase; /* Base address of the CAN filter registers */ + uint32_t baud; /* Configured baud */ +}; + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +/* CAN Register access */ + +static uint32_t gd32can_getreg(struct gd32_can_s *priv, + int offset); +static uint32_t gd32can_getfreg(struct gd32_can_s *priv, + int offset); +static void gd32can_putreg(struct gd32_can_s *priv, int offset, + uint32_t value); +static void gd32can_putfreg(struct gd32_can_s *priv, int offset, + uint32_t value); +#ifdef CONFIG_GD32F4_CAN_REGDEBUG +static void gd32can_dumpctrlregs(struct gd32_can_s *priv, + const char *msg); +static void gd32can_dumpmbregs(struct gd32_can_s *priv, + const char *msg); +static void gd32can_dumpfiltregs(struct gd32_can_s *priv, + const char *msg); +#else +# define gd32can_dumpctrlregs(priv,msg) +# define gd32can_dumpmbregs(priv,msg) +# define gd32can_dumpfiltregs(priv,msg) +#endif + +/* Filtering (todo) */ + +#ifdef CONFIG_CAN_EXTID +static int gd32can_addextfilter(struct gd32_can_s *priv, + struct canioc_extfilter_s *arg); +static int gd32can_delextfilter(struct gd32_can_s *priv, + int arg); +#endif +static int gd32can_addstdfilter(struct gd32_can_s *priv, + struct canioc_stdfilter_s *arg); +static int gd32can_delstdfilter(struct gd32_can_s *priv, + int arg); + +/* CAN driver methods */ + +static void gd32can_reset(struct can_dev_s *dev); +static int gd32can_setup(struct can_dev_s *dev); +static void gd32can_shutdown(struct can_dev_s *dev); +static void gd32can_rxint(struct can_dev_s *dev, bool enable); +static void gd32can_txint(struct can_dev_s *dev, bool enable); +static int gd32can_ioctl(struct can_dev_s *dev, int cmd, + unsigned long arg); +static int gd32can_remoterequest(struct can_dev_s *dev, + uint16_t id); +static int gd32can_send(struct can_dev_s *dev, + struct can_msg_s *msg); +static bool gd32can_txready(struct can_dev_s *dev); +static bool gd32can_txempty(struct can_dev_s *dev); + +#ifdef CONFIG_CAN_ERRORS +static void gd32can_errint(struct can_dev_s *dev, bool enable); +#endif + +/* CAN interrupt handling */ + +static int gd32can_rxinterrupt(struct can_dev_s *dev, int rxmb); +static int gd32can_rx0interrupt(int irq, void *context, void *arg); +static int gd32can_rx1interrupt(int irq, void *context, void *arg); +static int gd32can_txinterrupt(int irq, void *context, void *arg); +#ifdef CONFIG_CAN_ERRORS +static int gd32can_sceinterrupt(int irq, void *context, void *arg); +#endif + +/* Initialization */ + +static int gd32can_enterinitmode(struct gd32_can_s *priv); +static int gd32can_exitinitmode(struct gd32_can_s *priv); +static int gd32can_bittiming(struct gd32_can_s *priv); +static int gd32can_cellinit(struct gd32_can_s *priv); +static int gd32can_filterinit(struct gd32_can_s *priv); + +/* TX mailbox status */ + +static bool gd32can_txmb0empty(uint32_t tsr_regval); +static bool gd32can_txmb1empty(uint32_t tsr_regval); +static bool gd32can_txmb2empty(uint32_t tsr_regval); + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +static const struct can_ops_s g_canops = +{ + .co_reset = gd32can_reset, + .co_setup = gd32can_setup, + .co_shutdown = gd32can_shutdown, + .co_rxint = gd32can_rxint, + .co_txint = gd32can_txint, + .co_ioctl = gd32can_ioctl, + .co_remoterequest = gd32can_remoterequest, + .co_send = gd32can_send, + .co_txready = gd32can_txready, + .co_txempty = gd32can_txempty, +}; + +#ifdef CONFIG_GD32F4_CAN0 +static struct gd32_can_s g_can0priv = +{ + .port = 0, + .canrx = + { + GD32_IRQ_CAN0_RX0, + GD32_IRQ_CAN0_RX1, + }, + .cantx = GD32_IRQ_CAN0_TX, +#ifdef CONFIG_CAN_ERRORS + .cansce = GD32_IRQ_CAN0_EWMC, +#endif + .filter = 0, + .base = GD32_CAN0_BASE, + .fbase = GD32_CAN0_BASE, + .baud = CONFIG_GD32F4_CAN0_BAUD, +}; + +static struct can_dev_s g_can0dev = +{ + .cd_ops = &g_canops, + .cd_priv = &g_can0priv, +}; +#endif + +#ifdef CONFIG_GD32F4_CAN1 +static struct gd32_can_s g_can1priv = +{ + .port = 1, + .canrx = + { + GD32_IRQ_CAN1_RX0, + GD32_IRQ_CAN1_RX1, + }, + .cantx = GD32_IRQ_CAN1_TX, +#ifdef CONFIG_CAN_ERRORS + .cansce = GD32_IRQ_CAN1_EWMC, +#endif + .filter = CAN_NFILTERS / 2, + .base = GD32_CAN1_BASE, + .fbase = GD32_CAN0_BASE, + .baud = CONFIG_GD32F4_CAN1_BAUD, +}; + +static struct can_dev_s g_can1dev = +{ + .cd_ops = &g_canops, + .cd_priv = &g_can1priv, +}; +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: gd32can_getreg + * Name: gd32can_getfreg + * + * Description: + * Read the value of a CAN register or filter block register. + * + * Input Parameters: + * priv - A reference to the CAN block status + * offset - The offset to the register to read + * + * Returned Value: + * + ****************************************************************************/ + +#ifdef CONFIG_GD32F4_CAN_REGDEBUG +static uint32_t gd32can_vgetreg(uint32_t addr) +{ + static uint32_t prevaddr = 0; + static uint32_t preval = 0; + static uint32_t count = 0; + + /* Read the value from the register */ + + uint32_t val = getreg32(addr); + + /* Is this the same value that we read from the same register last time? + * Are we polling the register? If so, suppress some of the output. + */ + + if (addr == prevaddr && val == preval) + { + if (count == 0xffffffff || ++count > 3) + { + if (count == 4) + { + caninfo("...\n"); + } + + return val; + } + } + + /* No this is a new address or value */ + + else + { + /* Did we print "..." for the previous value? */ + + if (count > 3) + { + /* Yes.. then show how many times the value repeated */ + + caninfo("[repeats %" PRIu32 " more times]\n", count - 3); + } + + /* Save the new address, value, and count */ + + prevaddr = addr; + preval = val; + count = 1; + } + + /* Show the register value read */ + + caninfo("%08" PRIx32 "->%08" PRIx32 "\n", addr, val); + return val; +} + +static uint32_t gd32can_getreg(struct gd32_can_s *priv, int offset) +{ + return gd32can_vgetreg(priv->base + offset); +} + +static uint32_t gd32can_getfreg(struct gd32_can_s *priv, int offset) +{ + return gd32can_vgetreg(priv->fbase + offset); +} + +#else +static uint32_t gd32can_getreg(struct gd32_can_s *priv, int offset) +{ + return getreg32(priv->base + offset); +} + +static uint32_t gd32can_getfreg(struct gd32_can_s *priv, int offset) +{ + return getreg32(priv->fbase + offset); +} + +#endif + +/**************************************************************************** + * Name: gd32can_putreg + * Name: gd32can_putfreg + * + * Description: + * Set the value of a CAN register or filter block register. + * + * Input Parameters: + * priv - A reference to the CAN block status + * offset - The offset to the register to write + * value - The value to write to the register + * + * Returned Value: + * None + * + ****************************************************************************/ + +#ifdef CONFIG_GD32F4_CAN_REGDEBUG +static void gd32can_vputreg(uint32_t addr, uint32_t value) +{ + /* Show the register value being written */ + + caninfo("%08" PRIx32 "->%08" PRIx32 "\n", addr, value); + + /* Write the value */ + + putreg32(value, addr); +} + +static void gd32can_putreg(struct gd32_can_s *priv, int offset, + uint32_t value) +{ + gd32can_vputreg(priv->base + offset, value); +} + +static void gd32can_putfreg(struct gd32_can_s *priv, int offset, + uint32_t value) +{ + gd32can_vputreg(priv->fbase + offset, value); +} + +#else +static void gd32can_putreg(struct gd32_can_s *priv, int offset, + uint32_t value) +{ + putreg32(value, priv->base + offset); +} + +static void gd32can_putfreg(struct gd32_can_s *priv, int offset, + uint32_t value) +{ + putreg32(value, priv->fbase + offset); +} +#endif + +/**************************************************************************** + * Name: gd32can_dumpctrlregs + * + * Description: + * Dump the contents of all CAN control registers + * + * Input Parameters: + * priv - A reference to the CAN block status + * + * Returned Value: + * None + * + ****************************************************************************/ + +#ifdef CONFIG_GD32F4_CAN_REGDEBUG +static void gd32can_dumpctrlregs(struct gd32_can_s *priv, + const char *msg) +{ + if (msg) + { + caninfo("Control Registers: %s\n", msg); + } + else + { + caninfo("Control Registers:\n"); + } + + /* CAN control and status registers */ + + caninfo(" MCR: %08" PRIx32 " MSR: %08" PRIx32 " TSR: %08" PRIx32 "\n", + getreg32(priv->base + GD32_CAN_MCR_OFFSET), + getreg32(priv->base + GD32_CAN_MSR_OFFSET), + getreg32(priv->base + GD32_CAN_TSR_OFFSET)); + + caninfo(" RF0R: %08" PRIx32 " RF1R: %08" PRIx32 "\n", + getreg32(priv->base + GD32_CAN_RF0R_OFFSET), + getreg32(priv->base + GD32_CAN_RF1R_OFFSET)); + + caninfo(" IER: %08" PRIx32 " ESR: %08" PRIx32 " BTR: %08" PRIx32 "\n", + getreg32(priv->base + GD32_CAN_IER_OFFSET), + getreg32(priv->base + GD32_CAN_ESR_OFFSET), + getreg32(priv->base + GD32_CAN_BTR_OFFSET)); +} +#endif + +/**************************************************************************** + * Name: gd32can_dumpmbregs + * + * Description: + * Dump the contents of all CAN mailbox registers + * + * Input Parameters: + * priv - A reference to the CAN block status + * + * Returned Value: + * None + * + ****************************************************************************/ + +#ifdef CONFIG_GD32F4_CAN_REGDEBUG +static void gd32can_dumpmbregs(struct gd32_can_s *priv, + const char *msg) +{ + if (msg) + { + caninfo("Mailbox Registers: %s\n", msg); + } + else + { + caninfo("Mailbox Registers:\n"); + } + + /* CAN mailbox registers (3 TX and 2 RX) */ + + caninfo(" TI0R: %08" PRIx32 " TDT0R: %08" PRIx32 " TDL0R: %08" + PRIx32 " TDH0R: %08" PRIx32 "\n", + getreg32(priv->base + GD32_CAN_TI0R_OFFSET), + getreg32(priv->base + GD32_CAN_TDT0R_OFFSET), + getreg32(priv->base + GD32_CAN_TDL0R_OFFSET), + getreg32(priv->base + GD32_CAN_TDH0R_OFFSET)); + + caninfo(" TI1R: %08" PRIx32 " TDT1R: %08" PRIx32 " TDL1R: %08" + PRIx32 " TDH1R: %08" PRIx32 "\n", + getreg32(priv->base + GD32_CAN_TI1R_OFFSET), + getreg32(priv->base + GD32_CAN_TDT1R_OFFSET), + getreg32(priv->base + GD32_CAN_TDL1R_OFFSET), + getreg32(priv->base + GD32_CAN_TDH1R_OFFSET)); + + caninfo(" TI2R: %08" PRIx32 " TDT2R: %08" PRIx32 " TDL2R: %08" + PRIx32 " TDH2R: %08" PRIx32 "\n", + getreg32(priv->base + GD32_CAN_TI2R_OFFSET), + getreg32(priv->base + GD32_CAN_TDT2R_OFFSET), + getreg32(priv->base + GD32_CAN_TDL2R_OFFSET), + getreg32(priv->base + GD32_CAN_TDH2R_OFFSET)); + + caninfo(" RI0R: %08" PRIx32 " RDT0R: %08" PRIx32 " RDL0R: %08" + PRIx32 " RDH0R: %08" PRIx32 "\n", + getreg32(priv->base + GD32_CAN_RI0R_OFFSET), + getreg32(priv->base + GD32_CAN_RDT0R_OFFSET), + getreg32(priv->base + GD32_CAN_RDL0R_OFFSET), + getreg32(priv->base + GD32_CAN_RDH0R_OFFSET)); + + caninfo(" RI1R: %08" PRIx32 " RDT1R: %08" PRIx32 " RDL1R: %08" + PRIx32 " RDH1R: %08" PRIx32 "\n", + getreg32(priv->base + GD32_CAN_RI1R_OFFSET), + getreg32(priv->base + GD32_CAN_RDT1R_OFFSET), + getreg32(priv->base + GD32_CAN_RDL1R_OFFSET), + getreg32(priv->base + GD32_CAN_RDH1R_OFFSET)); +} +#endif + +/**************************************************************************** + * Name: gd32can_dumpfiltregs + * + * Description: + * Dump the contents of all CAN filter registers + * + * Input Parameters: + * priv - A reference to the CAN block status + * + * Returned Value: + * None + * + ****************************************************************************/ + +#ifdef CONFIG_GD32F4_CAN_REGDEBUG +static void gd32can_dumpfiltregs(struct gd32_can_s *priv, + const char *msg) +{ + int i; + + if (msg) + { + caninfo("Filter Registers: %s\n", msg); + } + else + { + caninfo("Filter Registers:\n"); + } + + caninfo(" FMR: %08" PRIx32 " FM1R: %08" PRIx32 " FS1R: %08" + PRIx32 " FFA1R: %08" PRIx32 " FA1R: %08" PRIx32 "\n", + getreg32(priv->base + GD32_CAN_FMR_OFFSET), + getreg32(priv->base + GD32_CAN_FM1R_OFFSET), + getreg32(priv->base + GD32_CAN_FS1R_OFFSET), + getreg32(priv->base + GD32_CAN_FFA1R_OFFSET), + getreg32(priv->base + GD32_CAN_FA1R_OFFSET)); + + for (i = 0; i < CAN_NFILTERS; i++) + { + caninfo(" F%dR1: %08" PRIx32 " F%dR2: %08" PRIx32 "\n", + i, getreg32(priv->base + GD32_CAN_FIR_OFFSET(i, 1)), + i, getreg32(priv->base + GD32_CAN_FIR_OFFSET(i, 2))); + } +} +#endif + +/**************************************************************************** + * Name: gd32can_reset + * + * Description: + * Reset the CAN device. Called early to initialize the hardware. This + * function is called, before gd32can_setup() and on error conditions. + * + * Input Parameters: + * dev - An instance of the "upper half" can driver state structure. + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void gd32can_reset(struct can_dev_s *dev) +{ + struct gd32_can_s *priv = dev->cd_priv; + uint32_t regval; + uint32_t regbit = 0; + irqstate_t flags; + + caninfo("CAN%" PRIu8 "\n", priv->port); + + /* Get the bits in the AHB1RSTR register needed to reset this CAN device */ + +#ifdef CONFIG_GD32F4_CAN0 + if (priv->port == 0) + { + regbit = RCU_APB1RST_CAN0RST; + } + else +#endif +#ifdef CONFIG_GD32F4_CAN1 + if (priv->port == 1) + { + regbit = RCU_APB1RST_CAN1RST; + } + else +#endif + { + canerr("ERROR: Unsupported port %d\n", priv->port); + return; + } + + /* Disable interrupts momentarily to stop any ongoing CAN event processing + * and to prevent any concurrent access to the AHB1RSTR register. + */ + + flags = enter_critical_section(); + + /* Reset the CAN */ + + regval = getreg32(GD32_RCU_APB1RST); + regval |= regbit; + putreg32(regval, GD32_RCU_APB1RST); + + regval &= ~regbit; + putreg32(regval, GD32_RCU_APB1RST); + leave_critical_section(flags); +} + +/**************************************************************************** + * Name: gd32can_setup + * + * Description: + * Configure the CAN. This method is called the first time that the CAN + * device is opened. This will occur when the port is first opened. + * This setup includes configuring and attaching CAN interrupts. + * All CAN interrupts are disabled upon return. + * + * Input Parameters: + * dev - An instance of the "upper half" can driver state structure. + * + * Returned Value: + * Zero on success; a negated errno on failure + * + ****************************************************************************/ + +static int gd32can_setup(struct can_dev_s *dev) +{ + struct gd32_can_s *priv = dev->cd_priv; + int ret; + +#ifdef CONFIG_CAN_ERRORS + ninfo("CAN%" PRIu8 " RX0 irq: %" PRIu8 " RX1 irq: %" PRIu8 + " TX irq: %" PRIu8 " SCE irq: %" PRIu8 "\n", + priv->port, priv->canrx[0], priv->canrx[1], priv->cantx, + priv->cansce); +#else + ninfo("CAN%" PRIu8 " RX0 irq: %" PRIu8 " RX1 irq: %" PRIu8 + " TX irq: %" PRIu8 "\n", + priv->port, priv->canrx[0], priv->canrx[1], priv->cantx); +#endif + + /* CAN cell initialization */ + + ret = gd32can_cellinit(priv); + if (ret < 0) + { + canerr("ERROR: CAN%" PRId8 " cell initialization failed: %d\n", + priv->port, ret); + return ret; + } + + gd32can_dumpctrlregs(priv, "After cell initialization"); + gd32can_dumpmbregs(priv, NULL); + + /* CAN filter initialization */ + + ret = gd32can_filterinit(priv); + if (ret < 0) + { + canerr("ERROR: CAN%" PRIu8 " filter initialization failed: %d\n", + priv->port, ret); + return ret; + } + + gd32can_dumpfiltregs(priv, "After filter initialization"); + + /* Attach the CAN RX FIFO 0/1 interrupts and TX interrupts. + * The others are not used. + */ + + ret = irq_attach(priv->canrx[0], gd32can_rx0interrupt, dev); + if (ret < 0) + { + canerr("ERROR: Failed to attach CAN%" PRIu8 " RX0 IRQ (%" PRIu8 ")", + priv->port, priv->canrx[0]); + return ret; + } + + ret = irq_attach(priv->canrx[1], gd32can_rx1interrupt, dev); + if (ret < 0) + { + canerr("ERROR: Failed to attach CAN%" PRIu8 " RX1 IRQ (%" PRIu8 ")", + priv->port, priv->canrx[1]); + return ret; + } + + ret = irq_attach(priv->cantx, gd32can_txinterrupt, dev); + if (ret < 0) + { + canerr("ERROR: Failed to attach CAN%" PRIu8 " TX IRQ (%" PRIu8 ")", + priv->port, priv->cantx); + return ret; + } + +#ifdef CONFIG_CAN_ERRORS + ret = irq_attach(priv->cansce, gd32can_sceinterrupt, dev); + if (ret < 0) + { + nerr("ERROR: Failed to attach CAN%" PRIu8 " SCE IRQ (%" PRIu8 ")", + priv->port, priv->cansce); + return ret; + } + + /* Enable CAN error interrupts */ + + gd32can_errint(dev, true); +#endif + + /* Enable the interrupts at the NVIC. Interrupts are still disabled in + * the CAN module. Since we coming out of reset here, there should be + * no pending interrupts. + */ + + up_enable_irq(priv->canrx[0]); + up_enable_irq(priv->canrx[1]); + up_enable_irq(priv->cantx); +#ifdef CONFIG_CAN_ERRORS + up_enable_irq(priv->cansce); +#endif + return OK; +} + +/**************************************************************************** + * Name: gd32can_shutdown + * + * Description: + * Disable the CAN. This method is called when the CAN device is closed. + * This method reverses the operation the setup method. + * + * Input Parameters: + * dev - An instance of the "upper half" can driver state structure. + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void gd32can_shutdown(struct can_dev_s *dev) +{ + struct gd32_can_s *priv = dev->cd_priv; + + caninfo("CAN%" PRIu8 "\n", priv->port); + + /* Disable the RX FIFO 0/1, TX and SCE interrupts */ + + up_disable_irq(priv->canrx[0]); + up_disable_irq(priv->canrx[1]); + up_disable_irq(priv->cantx); +#ifdef CONFIG_CAN_ERRORS + up_disable_irq(priv->cansce); +#endif + + /* Detach the RX FIFO 0/1, TX and SCE interrupts */ + + irq_detach(priv->canrx[0]); + irq_detach(priv->canrx[1]); + irq_detach(priv->cantx); +#ifdef CONFIG_CAN_ERRORS + irq_detach(priv->cansce); +#endif + + /* And reset the hardware */ + + gd32can_reset(dev); +} + +/**************************************************************************** + * Name: gd32can_rxint + * + * Description: + * Call to enable or disable RX interrupts. + * + * Input Parameters: + * dev - An instance of the "upper half" can driver state structure. + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void gd32can_rxint(struct can_dev_s *dev, bool enable) +{ + struct gd32_can_s *priv = dev->cd_priv; + uint32_t regval; + + caninfo("CAN%" PRIu8 " rxint enable: %d\n", priv->port, enable); + + /* Enable/disable the FIFO 0/1 message pending interrupt */ + + regval = gd32can_getreg(priv, GD32_CAN_IER_OFFSET); + if (enable) + { + regval |= CAN_IER_FMPIE0 | CAN_IER_FMPIE1; + } + else + { + regval &= ~(CAN_IER_FMPIE0 | CAN_IER_FMPIE1); + } + + gd32can_putreg(priv, GD32_CAN_IER_OFFSET, regval); +} + +/**************************************************************************** + * Name: gd32can_txint + * + * Description: + * Call to enable or disable TX interrupts. + * + * Input Parameters: + * dev - An instance of the "upper half" can driver state structure. + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void gd32can_txint(struct can_dev_s *dev, bool enable) +{ + struct gd32_can_s *priv = dev->cd_priv; + uint32_t regval; + + caninfo("CAN%" PRIu8 " txint enable: %d\n", priv->port, enable); + + /* Support only disabling the transmit mailbox interrupt */ + + if (!enable) + { + regval = gd32can_getreg(priv, GD32_CAN_IER_OFFSET); + regval &= ~CAN_IER_TMEIE; + gd32can_putreg(priv, GD32_CAN_IER_OFFSET, regval); + } +} + +#ifdef CONFIG_CAN_ERRORS +/**************************************************************************** + * Name: gd32can_errint + * + * Description: + * Call to enable or disable CAN error interrupts. + * + * Input Parameters: + * dev - An instance of the "upper half" can driver state structure. + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void gd32can_errint(struct can_dev_s *dev, bool enable) +{ + struct gd32_can_s *priv = dev->cd_priv; + uint32_t regval = 0; + + caninfo("CAN%" PRIu8 " errint enable: %d\n", priv->port, enable); + + /* Enable/disable the transmit mailbox interrupt */ + + regval = gd32can_getreg(priv, GD32_CAN_IER_OFFSET); + if (enable) + { + regval |= GD32_CAN_ERRINT; + } + else + { + regval &= ~GD32_CAN_ERRINT; + } + + gd32can_putreg(priv, GD32_CAN_IER_OFFSET, regval); +} +#endif + +/**************************************************************************** + * Name: gd32can_ioctl + * + * Description: + * All ioctl calls will be routed through this method + * + * Input Parameters: + * dev - An instance of the "upper half" can driver state structure. + * + * Returned Value: + * Zero on success; a negated errno on failure + * + ****************************************************************************/ + +static int gd32can_ioctl(struct can_dev_s *dev, int cmd, + unsigned long arg) +{ + struct gd32_can_s *priv; + int ret = -ENOTTY; + + caninfo("cmd=%04x arg=%lu\n", cmd, arg); + + DEBUGASSERT(dev && dev->cd_priv); + priv = dev->cd_priv; + + /* Handle the command */ + + switch (cmd) + { + /* CANIOC_GET_BITTIMING: + * Description: Return the current bit timing settings + * Argument: A pointer to a write-able instance of struct + * canioc_bittiming_s in which current bit timing + * values will be returned. + * Returned Value: Zero (OK) is returned on success. Otherwise -1 + * (ERROR) is returned with the errno variable set + * to indicate the nature of the error. + * Dependencies: None + */ + + case CANIOC_GET_BITTIMING: + { + struct canioc_bittiming_s *bt = + (struct canioc_bittiming_s *)arg; + uint32_t regval; + uint32_t brp; + + DEBUGASSERT(bt != NULL); + regval = gd32can_getreg(priv, GD32_CAN_BTR_OFFSET); + bt->bt_sjw = ((regval & CAN_BTR_SJW_MASK) >> + CAN_BTR_SJW_SHIFT) + 1; + bt->bt_tseg1 = ((regval & CAN_BTR_TS1_MASK) >> + CAN_BTR_TS1_SHIFT) + 1; + bt->bt_tseg2 = ((regval & CAN_BTR_TS2_MASK) >> + CAN_BTR_TS2_SHIFT) + 1; + + brp = ((regval & CAN_BTR_BRP_MASK) >> + CAN_BTR_BRP_SHIFT) + 1; + bt->bt_baud = GD32_PCLK1_FREQUENCY / + (brp * (bt->bt_tseg1 + bt->bt_tseg2 + 1)); + ret = OK; + } + break; + + /* CANIOC_SET_BITTIMING: + * Description: Set new current bit timing values + * Argument: A pointer to a read-able instance of struct + * canioc_bittiming_s in which the new bit timing + * values are provided. + * Returned Value: Zero (OK) is returned on success. Otherwise -1 + * (ERROR)is returned with the errno variable set + * to indicate thenature of the error. + * Dependencies: None + * + * REVISIT: There is probably a limitation here: If there are + * multiple threads trying to send CAN packets, when one of these + * threads reconfigures the bitrate, the MCAN hardware will be reset + * and the context of operation will be lost. Hence, this IOCTL can + * only safely be executed in quiescent time periods. + */ + + case CANIOC_SET_BITTIMING: + { + const struct canioc_bittiming_s *bt = + (const struct canioc_bittiming_s *)arg; + uint32_t brp; + uint32_t can_bit_quanta; + uint32_t tmp; + uint32_t regval; + + DEBUGASSERT(bt != NULL); + DEBUGASSERT(bt->bt_baud < GD32_PCLK1_FREQUENCY); + DEBUGASSERT(bt->bt_sjw > 0 && bt->bt_sjw <= 4); + DEBUGASSERT(bt->bt_tseg1 > 0 && bt->bt_tseg1 <= 16); + DEBUGASSERT(bt->bt_tseg2 > 0 && bt->bt_tseg2 <= 8); + + regval = gd32can_getreg(priv, GD32_CAN_BTR_OFFSET); + + /* Extract bit timing data + * tmp is in clocks per bit time + */ + + tmp = GD32_PCLK1_FREQUENCY / bt->bt_baud; + + /* This value is dynamic as requested by user */ + + can_bit_quanta = bt->bt_tseg1 + bt->bt_tseg2 + 1; + + if (tmp < can_bit_quanta) + { + /* This timing is not possible */ + + ret = -EINVAL; + break; + } + + /* Otherwise, nquanta is can_bit_quanta, ts1 and ts2 are + * provided by the user and we calculate brp to achieve + * can_bit_quanta quanta in the bit times + */ + + else + { + brp = (tmp + (can_bit_quanta / 2)) / can_bit_quanta; + DEBUGASSERT(brp >= 1 && brp <= CAN_BTR_BRP_MAX); + } + + caninfo("TS1: %"PRIu8 " TS2: %" PRIu8 " BRP: %" PRIu32 "\n", + bt->bt_tseg1, bt->bt_tseg2, brp); + + /* Configure bit timing. */ + + regval &= ~(CAN_BTR_BRP_MASK | CAN_BTR_TS1_MASK | + CAN_BTR_TS2_MASK | CAN_BTR_SJW_MASK); + regval |= ((brp - 1) << CAN_BTR_BRP_SHIFT) | + ((bt->bt_tseg1 - 1) << CAN_BTR_TS1_SHIFT) | + ((bt->bt_tseg2 - 1) << CAN_BTR_TS2_SHIFT) | + ((bt->bt_sjw - 1) << CAN_BTR_SJW_SHIFT); + + /* Bit timing can only be configured in init mode. */ + + ret = gd32can_enterinitmode(priv); + if (ret < 0) + { + break; + } + + gd32can_putreg(priv, GD32_CAN_BTR_OFFSET, regval); + + ret = gd32can_exitinitmode(priv); + if (ret >= 0) + { + priv->baud = GD32_PCLK1_FREQUENCY / + (brp * (bt->bt_tseg1 + bt->bt_tseg2 + 1)); + } + } + break; + + /* CANIOC_GET_CONNMODES: + * Description: Get the current bus connection modes + * Argument: A pointer to a write-able instance of struct + * canioc_connmodes_s in which the new bus modes will + * be returned. + * Returned Value: Zero (OK) is returned on success. Otherwise -1 + * (ERROR)is returned with the errno variable set + * to indicate the nature of the error. + * Dependencies: None + */ + + case CANIOC_GET_CONNMODES: + { + struct canioc_connmodes_s *bm = + (struct canioc_connmodes_s *)arg; + uint32_t regval; + + DEBUGASSERT(bm != NULL); + + regval = gd32can_getreg(priv, GD32_CAN_BTR_OFFSET); + + bm->bm_loopback = ((regval & CAN_BTR_LBKM) == CAN_BTR_LBKM); + bm->bm_silent = ((regval & CAN_BTR_SILM) == CAN_BTR_SILM); + ret = OK; + break; + } + + /* CANIOC_SET_CONNMODES: + * Description: Set new bus connection modes values + * Argument: A pointer to a read-able instance of struct + * canioc_connmodes_s in which the new bus modes + * are provided. + * Returned Value: Zero (OK) is returned on success. Otherwise -1 + * (ERROR) is returned with the errno variable set + * to indicate the nature of the error. + * Dependencies: None + */ + + case CANIOC_SET_CONNMODES: + { + struct canioc_connmodes_s *bm = + (struct canioc_connmodes_s *)arg; + uint32_t regval; + + DEBUGASSERT(bm != NULL); + + regval = gd32can_getreg(priv, GD32_CAN_BTR_OFFSET); + + if (bm->bm_loopback) + { + regval |= CAN_BTR_LBKM; + } + else + { + regval &= ~CAN_BTR_LBKM; + } + + if (bm->bm_silent) + { + regval |= CAN_BTR_SILM; + } + else + { + regval &= ~CAN_BTR_SILM; + } + + /* This register can only be configured in init mode. */ + + ret = gd32can_enterinitmode(priv); + if (ret < 0) + { + break; + } + + gd32can_putreg(priv, GD32_CAN_BTR_OFFSET, regval); + + ret = gd32can_exitinitmode(priv); + } + break; + +#ifdef CONFIG_CAN_EXTID + /* CANIOC_ADD_EXTFILTER: + * Description: Add an address filter for a extended 29 bit + * address. + * Argument: A reference to struct canioc_extfilter_s + * Returned Value: A non-negative filter ID is returned on success. + * Otherwise -1 (ERROR) is returned with the errno + * variable set to indicate the nature of the error. + */ + + case CANIOC_ADD_EXTFILTER: + { + DEBUGASSERT(arg != 0); + ret = gd32can_addextfilter(priv, + (struct canioc_extfilter_s *)arg); + } + break; + + /* CANIOC_DEL_EXTFILTER: + * Description: Remove an address filter for a standard 29 bit + * address. + * Argument: The filter index previously returned by the + * CANIOC_ADD_EXTFILTER command + * Returned Value: Zero (OK) is returned on success. Otherwise -1 + * (ERROR)is returned with the errno variable set + * to indicate the nature of the error. + */ + + case CANIOC_DEL_EXTFILTER: + { +#if 0 /* Unimplemented */ + DEBUGASSERT(arg <= priv->config->nextfilters); +#endif + ret = gd32can_delextfilter(priv, (int)arg); + } + break; +#endif + + /* CANIOC_ADD_STDFILTER: + * Description: Add an address filter for a standard 11 bit + * address. + * Argument: A reference to struct canioc_stdfilter_s + * Returned Value: A non-negative filter ID is returned on success. + * Otherwise -1 (ERROR) is returned with the errno + * variable set to indicate the nature of the error. + */ + + case CANIOC_ADD_STDFILTER: + { + DEBUGASSERT(arg != 0); + ret = gd32can_addstdfilter(priv, + (struct canioc_stdfilter_s *)arg); + } + break; + + /* CANIOC_DEL_STDFILTER: + * Description: Remove an address filter for a standard 11 bit + * address. + * Argument: The filter index previously returned by the + * CANIOC_ADD_STDFILTER command + * Returned Value: Zero (OK) is returned on success. Otherwise -1 + * (ERROR) is returned with the errno variable set + * to indicate the nature of the error. + */ + + case CANIOC_DEL_STDFILTER: + { +#if 0 /* Unimplemented */ + DEBUGASSERT(arg <= priv->config->nstdfilters); +#endif + ret = gd32can_delstdfilter(priv, (int)arg); + } + break; + + case CANIOC_SET_NART: + { + uint32_t regval; + + ret = gd32can_enterinitmode(priv); + if (ret != 0) + { + return ret; + } + + regval = gd32can_getreg(priv, GD32_CAN_MCR_OFFSET); + if (arg == 1) + { + regval |= CAN_MCR_NART; + } + else + { + regval &= ~CAN_MCR_NART; + } + + gd32can_putreg(priv, GD32_CAN_MCR_OFFSET, regval); + return gd32can_exitinitmode(priv); + } + break; + + case CANIOC_SET_ABOM: + { + uint32_t regval; + + ret = gd32can_enterinitmode(priv); + if (ret != 0) + { + return ret; + } + + regval = gd32can_getreg(priv, GD32_CAN_MCR_OFFSET); + if (arg == 1) + { + regval |= CAN_MCR_ABOM; + } + else + { + regval &= ~CAN_MCR_ABOM; + } + + gd32can_putreg(priv, GD32_CAN_MCR_OFFSET, regval); + return gd32can_exitinitmode(priv); + } + break; + + /* Unsupported/unrecognized command */ + + default: + canerr("ERROR: Unrecognized command: %04x\n", cmd); + break; + } + + return ret; +} + +/**************************************************************************** + * Name: gd32can_remoterequest + * + * Description: + * Send a remote request + * + * Input Parameters: + * dev - An instance of the "upper half" can driver state structure. + * + * Returned Value: + * Zero on success; a negated errno on failure + * + ****************************************************************************/ + +static int gd32can_remoterequest(struct can_dev_s *dev, uint16_t id) +{ +#warning "Remote request not implemented" + return -ENOSYS; +} + +/**************************************************************************** + * Name: gd32can_send + * + * Description: + * Send one can message. + * + * One CAN-message consists of a maximum of 10 bytes. A message is + * composed of at least the first 2 bytes (when there are no data bytes). + * + * Byte 0: Bits 0-7: Bits 3-10 of the 11-bit CAN identifier + * Byte 1: Bits 5-7: Bits 0-2 of the 11-bit CAN identifier + * Bit 4: Remote Transmission Request (RTR) + * Bits 0-3: Data Length Code (DLC) + * Bytes 2-10: CAN data + * + * Input Parameters: + * dev - An instance of the "upper half" can driver state structure. + * + * Returned Value: + * Zero on success; a negated errno on failure + * + ****************************************************************************/ + +static int gd32can_send(struct can_dev_s *dev, + struct can_msg_s *msg) +{ + struct gd32_can_s *priv = dev->cd_priv; + uint8_t *ptr; + uint32_t regval; + uint32_t tmp; + int dlc; + int txmb; + + caninfo("CAN%" PRIu8 " ID: %" PRIu32 " DLC: %" PRIu8 "\n", + priv->port, (uint32_t)msg->cm_hdr.ch_id, msg->cm_hdr.ch_dlc); + + /* Select one empty transmit mailbox */ + + regval = gd32can_getreg(priv, GD32_CAN_TSR_OFFSET); + if (gd32can_txmb0empty(regval)) + { + txmb = 0; + } + else if (gd32can_txmb1empty(regval)) + { + txmb = 1; + } + else if (gd32can_txmb2empty(regval)) + { + txmb = 2; + } + else + { + canerr("ERROR: No available mailbox\n"); + return -EBUSY; + } + + /* Clear TXRQ, RTR, IDE, EXID, and STID fields */ + + regval = gd32can_getreg(priv, GD32_CAN_TIR_OFFSET(txmb)); + regval &= ~(CAN_TIR_TXRQ | CAN_TIR_RTR | CAN_TIR_IDE | + CAN_TIR_EXID_MASK | CAN_TIR_STID_MASK); + gd32can_putreg(priv, GD32_CAN_TIR_OFFSET(txmb), regval); + + /* Set up the ID, standard 11-bit or extended 29-bit. */ + +#ifdef CONFIG_CAN_EXTID + regval &= ~CAN_TIR_EXID_MASK; + if (msg->cm_hdr.ch_extid) + { + DEBUGASSERT(msg->cm_hdr.ch_id < (1 << 29)); + regval |= (msg->cm_hdr.ch_id << CAN_TIR_EXID_SHIFT) | CAN_TIR_IDE; + } + else + { + DEBUGASSERT(msg->cm_hdr.ch_id < (1 << 11)); + regval |= msg->cm_hdr.ch_id << CAN_TIR_STID_SHIFT; + } + +#else + regval |= (((uint32_t) msg->cm_hdr.ch_id << CAN_TIR_STID_SHIFT) & + CAN_TIR_STID_MASK); + +#endif + +#ifdef CONFIG_CAN_USE_RTR + regval |= (msg->cm_hdr.ch_rtr ? CAN_TIR_RTR : 0); +#endif + + gd32can_putreg(priv, GD32_CAN_TIR_OFFSET(txmb), regval); + + /* Set up the DLC */ + + dlc = msg->cm_hdr.ch_dlc; + regval = gd32can_getreg(priv, GD32_CAN_TDTR_OFFSET(txmb)); + regval &= ~(CAN_TDTR_DLC_MASK | CAN_TDTR_TGT); + regval |= (uint32_t)dlc << CAN_TDTR_DLC_SHIFT; + gd32can_putreg(priv, GD32_CAN_TDTR_OFFSET(txmb), regval); + + /* Set up the data fields */ + + ptr = msg->cm_data; + regval = 0; + + if (dlc > 0) + { + tmp = (uint32_t)*ptr++; + regval = tmp << CAN_TDLR_DATA0_SHIFT; + + if (dlc > 1) + { + tmp = (uint32_t)*ptr++; + regval |= tmp << CAN_TDLR_DATA1_SHIFT; + + if (dlc > 2) + { + tmp = (uint32_t)*ptr++; + regval |= tmp << CAN_TDLR_DATA2_SHIFT; + + if (dlc > 3) + { + tmp = (uint32_t)*ptr++; + regval |= tmp << CAN_TDLR_DATA3_SHIFT; + } + } + } + } + + gd32can_putreg(priv, GD32_CAN_TDLR_OFFSET(txmb), regval); + + regval = 0; + if (dlc > 4) + { + tmp = (uint32_t)*ptr++; + regval = tmp << CAN_TDHR_DATA4_SHIFT; + + if (dlc > 5) + { + tmp = (uint32_t)*ptr++; + regval |= tmp << CAN_TDHR_DATA5_SHIFT; + + if (dlc > 6) + { + tmp = (uint32_t)*ptr++; + regval |= tmp << CAN_TDHR_DATA6_SHIFT; + + if (dlc > 7) + { + tmp = (uint32_t)*ptr++; + regval |= tmp << CAN_TDHR_DATA7_SHIFT; + } + } + } + } + + gd32can_putreg(priv, GD32_CAN_TDHR_OFFSET(txmb), regval); + + /* Enable the transmit mailbox empty interrupt (may already be enabled) */ + + regval = gd32can_getreg(priv, GD32_CAN_IER_OFFSET); + regval |= CAN_IER_TMEIE; + gd32can_putreg(priv, GD32_CAN_IER_OFFSET, regval); + + /* Request transmission */ + + regval = gd32can_getreg(priv, GD32_CAN_TIR_OFFSET(txmb)); + regval |= CAN_TIR_TXRQ; /* Transmit Mailbox Request */ + gd32can_putreg(priv, GD32_CAN_TIR_OFFSET(txmb), regval); + + gd32can_dumpmbregs(priv, "After send"); + return OK; +} + +/**************************************************************************** + * Name: gd32can_txready + * + * Description: + * Return true if the CAN hardware can accept another TX message. + * + * Input Parameters: + * dev - An instance of the "upper half" can driver state structure. + * + * Returned Value: + * True if the CAN hardware is ready to accept another TX message. + * + ****************************************************************************/ + +static bool gd32can_txready(struct can_dev_s *dev) +{ + struct gd32_can_s *priv = dev->cd_priv; + uint32_t regval; + + /* Return true if any mailbox is available */ + + regval = gd32can_getreg(priv, GD32_CAN_TSR_OFFSET); + caninfo("CAN%" PRIu8 " TSR: %08" PRIx32 "\n", priv->port, regval); + + return gd32can_txmb0empty(regval) || gd32can_txmb1empty(regval) || + gd32can_txmb2empty(regval); +} + +/**************************************************************************** + * Name: gd32can_txempty + * + * Description: + * Return true if all message have been sent. If for example, the CAN + * hardware implements FIFOs, then this would mean the transmit FIFO is + * empty. This method is called when the driver needs to make sure that + * all characters are "drained" from the TX hardware before calling + * co_shutdown(). + * + * Input Parameters: + * dev - An instance of the "upper half" can driver state structure. + * + * Returned Value: + * True if there are no pending TX transfers in the CAN hardware. + * + ****************************************************************************/ + +static bool gd32can_txempty(struct can_dev_s *dev) +{ + struct gd32_can_s *priv = dev->cd_priv; + uint32_t regval; + + /* Return true if all mailboxes are available */ + + regval = gd32can_getreg(priv, GD32_CAN_TSR_OFFSET); + caninfo("CAN%" PRIu8 " TSR: %08" PRIx32 "\n", priv->port, regval); + + return gd32can_txmb0empty(regval) && gd32can_txmb1empty(regval) && + gd32can_txmb2empty(regval); +} + +/**************************************************************************** + * Name: gd32can_rxinterrupt + * + * Description: + * CAN RX FIFO 0/1 interrupt handler + * + * Input Parameters: + * irq - The IRQ number of the interrupt. + * context - The register state save array at the time of the interrupt. + * rxmb - The RX mailbox number. + * + * Returned Value: + * Zero on success; a negated errno on failure + * + ****************************************************************************/ + +static int gd32can_rxinterrupt(struct can_dev_s *dev, int rxmb) +{ + struct gd32_can_s *priv; + struct can_hdr_s hdr; + uint8_t data[CAN_MAXDATALEN]; + uint32_t regval; + int npending; + int ret; + + DEBUGASSERT(dev != NULL && dev->cd_priv != NULL); + priv = dev->cd_priv; + + /* Verify that a message is pending in the FIFO */ + + regval = gd32can_getreg(priv, GD32_CAN_RFR_OFFSET(rxmb)); + npending = (regval & CAN_RFR_FMP_MASK) >> CAN_RFR_FMP_SHIFT; + if (npending < 1) + { + canwarn("WARNING: No messages pending\n"); + return OK; + } + + if (rxmb == 0) + { + gd32can_dumpmbregs(priv, "RX0 interrupt"); + } + else + { + gd32can_dumpmbregs(priv, "RX1 interrupt"); + } + + /* Get the CAN identifier. */ + + regval = gd32can_getreg(priv, GD32_CAN_RIR_OFFSET(rxmb)); + +#ifdef CONFIG_CAN_EXTID + if ((regval & CAN_RIR_IDE) != 0) + { + hdr.ch_id = (regval & CAN_RIR_EXID_MASK) >> CAN_RIR_EXID_SHIFT; + hdr.ch_extid = true; + } + else + { + hdr.ch_id = (regval & CAN_RIR_STID_MASK) >> CAN_RIR_STID_SHIFT; + hdr.ch_extid = false; + } +#else + if ((regval & CAN_RIR_IDE) != 0) + { + canerr("ERROR: Received message with extended identifier. Dropped\n"); + ret = -ENOSYS; + goto errout; + } + + hdr.ch_id = (regval & CAN_RIR_STID_MASK) >> CAN_RIR_STID_SHIFT; +#endif + + /* Clear the error indication and unused bits */ + +#ifdef CONFIG_CAN_ERRORS + hdr.ch_error = 0; /* Error reporting not supported */ +#endif + hdr.ch_tcf = 0; + + /* Extract the RTR bit */ + + hdr.ch_rtr = (regval & CAN_RIR_RTR) != 0; + + /* Get the DLC */ + + regval = gd32can_getreg(priv, GD32_CAN_RDTR_OFFSET(rxmb)); + hdr.ch_dlc = (regval & CAN_RDTR_DLC_MASK) >> CAN_RDTR_DLC_SHIFT; + + /* Save the message data */ + + regval = gd32can_getreg(priv, GD32_CAN_RDLR_OFFSET(rxmb)); + data[0] = (regval & CAN_RDLR_DATA0_MASK) >> CAN_RDLR_DATA0_SHIFT; + data[1] = (regval & CAN_RDLR_DATA1_MASK) >> CAN_RDLR_DATA1_SHIFT; + data[2] = (regval & CAN_RDLR_DATA2_MASK) >> CAN_RDLR_DATA2_SHIFT; + data[3] = (regval & CAN_RDLR_DATA3_MASK) >> CAN_RDLR_DATA3_SHIFT; + + regval = gd32can_getreg(priv, GD32_CAN_RDHR_OFFSET(rxmb)); + data[4] = (regval & CAN_RDHR_DATA4_MASK) >> CAN_RDHR_DATA4_SHIFT; + data[5] = (regval & CAN_RDHR_DATA5_MASK) >> CAN_RDHR_DATA5_SHIFT; + data[6] = (regval & CAN_RDHR_DATA6_MASK) >> CAN_RDHR_DATA6_SHIFT; + data[7] = (regval & CAN_RDHR_DATA7_MASK) >> CAN_RDHR_DATA7_SHIFT; + + /* Provide the data to the upper half driver */ + + ret = can_receive(dev, &hdr, data); + + /* Release the FIFO */ + +#ifndef CONFIG_CAN_EXTID +errout: +#endif + regval = gd32can_getreg(priv, GD32_CAN_RFR_OFFSET(rxmb)); + regval |= CAN_RFR_RFOM; + gd32can_putreg(priv, GD32_CAN_RFR_OFFSET(rxmb), regval); + return ret; +} + +/**************************************************************************** + * Name: gd32can_rx0interrupt + * + * Description: + * CAN RX FIFO 0 interrupt handler + * + * Input Parameters: + * irq - The IRQ number of the interrupt. + * context - The register state save array at the time of the interrupt. + * + * Returned Value: + * Zero on success; a negated errno on failure + * + ****************************************************************************/ + +static int gd32can_rx0interrupt(int irq, void *context, void *arg) +{ + struct can_dev_s *dev = (struct can_dev_s *)arg; + return gd32can_rxinterrupt(dev, 0); +} + +/**************************************************************************** + * Name: gd32can_rx1interrupt + * + * Description: + * CAN RX FIFO 1 interrupt handler + * + * Input Parameters: + * irq - The IRQ number of the interrupt. + * context - The register state save array at the time of the interrupt. + * + * Returned Value: + * Zero on success; a negated errno on failure + * + ****************************************************************************/ + +static int gd32can_rx1interrupt(int irq, void *context, void *arg) +{ + struct can_dev_s *dev = (struct can_dev_s *)arg; + return gd32can_rxinterrupt(dev, 1); +} + +/**************************************************************************** + * Name: gd32can_txinterrupt + * + * Description: + * CAN TX mailbox complete interrupt handler + * + * Input Parameters: + * irq - The IRQ number of the interrupt. + * context - The register state save array at the time of the interrupt. + * + * Returned Value: + * Zero on success; a negated errno on failure + * + ****************************************************************************/ + +static int gd32can_txinterrupt(int irq, void *context, void *arg) +{ + struct can_dev_s *dev = (struct can_dev_s *)arg; + struct gd32_can_s *priv; + uint32_t regval; + + DEBUGASSERT(dev != NULL && dev->cd_priv != NULL); + priv = dev->cd_priv; + + /* Get the transmit status */ + + regval = gd32can_getreg(priv, GD32_CAN_TSR_OFFSET); + + /* Check for RQCP0: Request completed mailbox 0 */ + + if ((regval & CAN_TSR_RQCP0) != 0) + { + /* Writing '1' to RCP0 clears RCP0 and all the status bits (TXOK0, + * ALST0 and TERR0) for Mailbox 0. + */ + + gd32can_putreg(priv, GD32_CAN_TSR_OFFSET, CAN_TSR_RQCP0); + + /* Tell the upper half that the transfer is finished. */ + + can_txdone(dev); + } + + /* Check for RQCP1: Request completed mailbox 1 */ + + if ((regval & CAN_TSR_RQCP1) != 0) + { + /* Writing '1' to RCP1 clears RCP1 and all the status bits (TXOK1, + * ALST1 and TERR1) for Mailbox 1. + */ + + gd32can_putreg(priv, GD32_CAN_TSR_OFFSET, CAN_TSR_RQCP1); + + /* Tell the upper half that the transfer is finished. */ + + can_txdone(dev); + } + + /* Check for RQCP2: Request completed mailbox 2 */ + + if ((regval & CAN_TSR_RQCP2) != 0) + { + /* Writing '1' to RCP2 clears RCP2 and all the status bits (TXOK2, + * ALST2 and TERR2) for Mailbox 2. + */ + + gd32can_putreg(priv, GD32_CAN_TSR_OFFSET, CAN_TSR_RQCP2); + + /* Tell the upper half that the transfer is finished. */ + + can_txdone(dev); + } + + return OK; +} + +#ifdef CONFIG_CAN_ERRORS +/**************************************************************************** + * Name: gd32can_sceinterrupt + * + * Description: + * CAN status change interrupt handler + * + * Input Parameters: + * irq - The IRQ number of the interrupt. + * context - The register state save array at the time of the interrupt. + * + * Returned Value: + * Zero on success; a negated errno on failure + * + ****************************************************************************/ + +static int gd32can_sceinterrupt(int irq, void *context, void *arg) +{ + struct can_dev_s *dev = (struct can_dev_s *)arg; + struct gd32_can_s *priv = NULL; + struct can_hdr_s hdr; + uint32_t regval = 0; + uint16_t errbits = 0; + uint8_t data[CAN_ERROR_DLC]; + int ret = OK; + + DEBUGASSERT(dev != NULL && dev->cd_priv != NULL); + priv = dev->cd_priv; + + /* Check Error Interrupt flag */ + + regval = gd32can_getreg(priv, GD32_CAN_MSR_OFFSET); + if (regval & CAN_MSR_ERRI) + { + /* Encode error bits */ + + errbits = 0; + memset(data, 0, sizeof(data)); + + /* Get Error statur register */ + + regval = gd32can_getreg(priv, GD32_CAN_ESR_OFFSET); + + if (regval & CAN_ESR_EWGF) + { + /* Error warning flag */ + + data[1] |= (CAN_ERROR1_RXWARNING | CAN_ERROR1_TXWARNING); + errbits |= CAN_ERROR_CONTROLLER; + } + + if (regval & CAN_ESR_EPVF) + { + /* Error passive flag */ + + data[1] |= (CAN_ERROR1_RXPASSIVE | CAN_ERROR1_TXPASSIVE); + errbits |= CAN_ERROR_CONTROLLER; + } + + if (regval & CAN_ESR_BOFF) + { + /* Bus-off flag */ + + errbits |= CAN_ERROR_BUSOFF; + } + + /* Last error code */ + + if (regval & CAN_ESR_LEC_MASK) + { + if (regval & CAN_ESR_STUFFERROR) + { + /* Stuff Error */ + + errbits |= CAN_ERROR_PROTOCOL; + data[2] |= CAN_ERROR2_STUFF; + } + else if (regval & CAN_ESR_FORMERROR) + { + /* Format Error */ + + errbits |= CAN_ERROR_PROTOCOL; + data[2] |= CAN_ERROR2_FORM; + } + else if (regval & CAN_ESR_ACKERROR) + { + /* Acknowledge Error */ + + errbits |= CAN_ERROR_NOACK; + } + else if (regval & CAN_ESR_BRECERROR) + { + /* Bit recessive Error */ + + errbits |= CAN_ERROR_PROTOCOL; + data[2] |= CAN_ERROR2_BIT1; + } + else if (regval & CAN_ESR_BDOMERROR) + { + /* Bit dominant Error */ + + errbits |= CAN_ERROR_PROTOCOL; + data[2] |= CAN_ERROR2_BIT0; + } + else if (regval & CAN_ESR_CRCERRPR) + { + /* Receive CRC Error */ + + errbits |= CAN_ERROR_PROTOCOL; + data[3] |= CAN_ERROR3_CRCSEQ; + } + } + + /* Get transmit status register */ + + regval = gd32can_getreg(priv, GD32_CAN_TSR_OFFSET); + + if (regval & CAN_TSR_ALST0 || regval & CAN_TSR_ALST1 || + regval & CAN_TSR_ALST2) + { + /* Lost arbitration Error */ + + errbits |= CAN_ERROR_LOSTARB; + } + + /* Clear TSR register */ + + gd32can_putreg(priv, GD32_CAN_TSR_OFFSET, regval); + + /* Clear ERRI flag */ + + gd32can_putreg(priv, GD32_CAN_MSR_OFFSET, CAN_MSR_ERRI); + } + + /* TODO: RX overflow and TX overflow */ + + /* Report a CAN error */ + + if (errbits != 0) + { + canerr("ERROR: errbits = %08" PRIx16 "\n", errbits); + + /* Format the CAN header for the error report. */ + + hdr.ch_id = errbits; + hdr.ch_dlc = CAN_ERROR_DLC; + hdr.ch_rtr = 0; + hdr.ch_error = 1; +#ifdef CONFIG_CAN_EXTID + hdr.ch_extid = 0; +#endif + hdr.ch_tcf = 0; + + /* And provide the error report to the upper half logic */ + + ret = can_receive(dev, &hdr, data); + if (ret < 0) + { + canerr("ERROR: can_receive failed: %d\n", ret); + } + } + + return ret; +} +#endif + +/**************************************************************************** + * Name: gd32can_bittiming + * + * Description: + * Set the CAN bit timing register (BTR) based on the configured BAUD. + * + * "The bit timing logic monitors the serial bus-line and performs sampling + * and adjustment of the sample point by synchronizing on the start-bit edge + * and resynchronizing on the following edges. + * + * "Its operation may be explained simply by splitting nominal bit time into + * three segments as follows: + * + * 1. "Synchronization segment (SYNC_SEG): a bit change is expected to occur + * within this time segment. It has a fixed length of one time quantum + * (1 x tCAN). + * 2. "Bit segment 1 (BS1): defines the location of the sample point. It + * includes the PROP_SEG and PHASE_SEG1 of the CAN standard. Its duration + * is programmable between 1 and 16 time quanta but may be automatically + * lengthened to compensate for positive phase drifts due to differences + * in the frequency of the various nodes of the network. + * 3. "Bit segment 2 (BS2): defines the location of the transmit point. It + * represents the PHASE_SEG2 of the CAN standard. Its duration is + * programmable between 1 and 8 time quanta but may also be automatically + * shortened to compensate for negative phase drifts." + * + * Pictorially: + * + * |<----------------- NOMINAL BIT TIME ----------------->| + * |<- SYNC_SEG ->|<------ BS1 ------>|<------ BS2 ------>| + * |<---- Tq ---->|<----- Tbs1 ------>|<----- Tbs2 ------>| + * + * Where + * Tbs1 is the duration of the BS1 segment + * Tbs2 is the duration of the BS2 segment + * Tq is the "Time Quantum" + * + * Relationships: + * + * baud = 1 / bit_time + * bit_time = Tq + Tbs1 + Tbs2 + * Tbs1 = Tq * ts1 + * Tbs2 = Tq * ts2 + * Tq = brp * Tpclk1 + * baud = Fpclk1 / (brp * (1 + ts1 + ts2)) + * + * Where: + * Tpclk1 is the period of the APB1 clock (PCLK1). + * + * Input Parameters: + * priv - A reference to the CAN block status + * + * Returned Value: + * Zero on success; a negated errno on failure + * + ****************************************************************************/ + +static int gd32can_bittiming(struct gd32_can_s *priv) +{ + uint32_t tmp; + uint32_t brp; + uint32_t ts1; + uint32_t ts2; + + caninfo("CAN%" PRIu8 " PCLK1: %lu baud: %" PRIu32 "\n", + priv->port, (unsigned long) GD32_PCLK1_FREQUENCY, priv->baud); + + /* Try to get CAN_BIT_QUANTA quanta in one bit_time. + * + * bit_time = Tq*(ts1 + ts2 + 1) + * nquanta = bit_time / Tq + * nquanta = (ts1 + ts2 + 1) + * + * bit_time = brp * Tpclk1 * (ts1 + ts2 + 1) + * nquanta = bit_time / brp / Tpclk1 + * = PCLK1 / baud / brp + * brp = PCLK1 / baud / nquanta; + * + * Example: + * PCLK1 = 42,000,000 baud = 1,000,000 nquanta = 14 : brp = 3 + * PCLK1 = 42,000,000 baud = 700,000 nquanta = 14 : brp = 4 + */ + + tmp = GD32_PCLK1_FREQUENCY / priv->baud; + if (tmp < CAN_BIT_QUANTA) + { + /* At the smallest brp value (1), there are already too few bit times + * (PCLCK1 / baud) to meet our goal. brp must be one and we need + * make some reasonable guesses about ts1 and ts2. + */ + + brp = 1; + + /* In this case, we have to guess a good value for ts1 and ts2 */ + + ts1 = (tmp - 1) >> 1; + ts2 = tmp - ts1 - 1; + if (ts1 == ts2 && ts1 > 1 && ts2 < CAN_BTR_TSEG2_MAX) + { + ts1--; + ts2++; + } + } + + /* Otherwise, nquanta is CAN_BIT_QUANTA, ts1 is CONFIG_GD32F4_CAN_TSEG1, + * ts2 is CONFIG_GD32F4_CAN_TSEG2 and we calculate brp to achieve + * CAN_BIT_QUANTA quanta in the bit time + */ + + else + { + ts1 = CONFIG_GD32F4_CAN_TSEG1; + ts2 = CONFIG_GD32F4_CAN_TSEG2; + brp = (tmp + (CAN_BIT_QUANTA / 2)) / CAN_BIT_QUANTA; + DEBUGASSERT(brp >= 1 && brp <= CAN_BTR_BRP_MAX); + } + + caninfo("TS1: %" PRIu32 " TS2: %" PRIu32 " BRP: %" PRIu32 "\n", + ts1, ts2, brp); + + /* Configure bit timing. This also does the following, less obvious + * things. Unless loopback mode is enabled, it: + * + * - Disables silent mode. + * - Disables loopback mode. + * + * NOTE that for the time being, SJW is set to 1 just because I don't + * know any better. + */ + + tmp = ((brp - 1) << CAN_BTR_BRP_SHIFT) | ((ts1 - 1) << CAN_BTR_TS1_SHIFT) | + ((ts2 - 1) << CAN_BTR_TS2_SHIFT) | ((1 - 1) << CAN_BTR_SJW_SHIFT); +#ifdef CONFIG_CAN_LOOPBACK + /* tmp |= (CAN_BTR_LBKM | CAN_BTR_SILM); */ + + tmp |= CAN_BTR_LBKM; +#endif + + gd32can_putreg(priv, GD32_CAN_BTR_OFFSET, tmp); + return OK; +} + +/**************************************************************************** + * Name: gd32can_enterinitmode + * + * Description: + * Put the CAN cell in Initialization mode. This only disconnects the CAN + * peripheral, no registers are changed. The initialization mode is + * required to change the baud rate. + * + * Input Parameters: + * priv - A pointer to the private data structure for this CAN block + * + * Returned Value: + * Zero on success; a negated errno value on failure. + * + ****************************************************************************/ + +static int gd32can_enterinitmode(struct gd32_can_s *priv) +{ + uint32_t regval; + volatile uint32_t timeout; + + caninfo("CAN%" PRIu8 "\n", priv->port); + + /* Enter initialization mode */ + + regval = gd32can_getreg(priv, GD32_CAN_MCR_OFFSET); + regval |= CAN_MCR_INRQ; + gd32can_putreg(priv, GD32_CAN_MCR_OFFSET, regval); + + /* Wait until initialization mode is acknowledged */ + + for (timeout = INAK_TIMEOUT; timeout > 0; timeout--) + { + regval = gd32can_getreg(priv, GD32_CAN_MSR_OFFSET); + if ((regval & CAN_MSR_INAK) != 0) + { + /* We are in initialization mode */ + + break; + } + } + + /* Check for a timeout */ + + if (timeout < 1) + { + canerr("ERROR: Timed out waiting to enter initialization mode\n"); + return -ETIMEDOUT; + } + + return OK; +} + +/**************************************************************************** + * Name: gd32can_exitinitmode + * + * Description: + * Put the CAN cell out of the Initialization mode (to Normal mode) + * + * Input Parameters: + * priv - A pointer to the private data structure for this CAN block + * + * Returned Value: + * Zero on success; a negated errno value on failure. + * + ****************************************************************************/ + +static int gd32can_exitinitmode(struct gd32_can_s *priv) +{ + uint32_t regval; + volatile uint32_t timeout; + + /* Exit Initialization mode, enter Normal mode */ + + regval = gd32can_getreg(priv, GD32_CAN_MCR_OFFSET); + regval &= ~CAN_MCR_INRQ; + gd32can_putreg(priv, GD32_CAN_MCR_OFFSET, regval); + + /* Wait until the initialization mode exit is acknowledged */ + + for (timeout = INAK_TIMEOUT; timeout > 0; timeout--) + { + regval = gd32can_getreg(priv, GD32_CAN_MSR_OFFSET); + if ((regval & CAN_MSR_INAK) == 0) + { + /* We are out of initialization mode */ + + break; + } + } + + /* Check for a timeout */ + + if (timeout < 1) + { + canerr("ERROR: Timed out waiting to exit initialization mode: %08" + PRIx32 "\n", regval); + return -ETIMEDOUT; + } + + return OK; +} + +/**************************************************************************** + * Name: gd32can_cellinit + * + * Description: + * CAN cell initialization + * + * Input Parameters: + * priv - A pointer to the private data structure for this CAN block + * + * Returned Value: + * Zero on success; a negated errno value on failure. + * + ****************************************************************************/ + +static int gd32can_cellinit(struct gd32_can_s *priv) +{ + uint32_t regval; + int ret; + + caninfo("CAN%" PRIu8 "\n", priv->port); + + /* Exit from sleep mode */ + + regval = gd32can_getreg(priv, GD32_CAN_MCR_OFFSET); + regval &= ~CAN_MCR_SLEEP; + gd32can_putreg(priv, GD32_CAN_MCR_OFFSET, regval); + + ret = gd32can_enterinitmode(priv); + if (ret != 0) + { + return ret; + } + + /* Disable the following modes: + * + * - Time triggered communication mode + * - Automatic bus-off management + * - Automatic wake-up mode + * - No automatic retransmission + * - Receive FIFO locked mode + * + * Enable: + * + * - Transmit FIFO priority + */ + + regval = gd32can_getreg(priv, GD32_CAN_MCR_OFFSET); + regval &= ~(CAN_MCR_RFLM | CAN_MCR_NART | CAN_MCR_AWUM | + CAN_MCR_ABOM | CAN_MCR_TTCM); + regval |= CAN_MCR_TXFP; + gd32can_putreg(priv, GD32_CAN_MCR_OFFSET, regval); + + /* Configure bit timing. */ + + ret = gd32can_bittiming(priv); + if (ret < 0) + { + canerr("ERROR: Failed to set bit timing: %d\n", ret); + return ret; + } + + return gd32can_exitinitmode(priv); +} + +/**************************************************************************** + * Name: gd32can_filterinit + * + * Description: + * CAN filter initialization. CAN filters are not currently used by this + * driver. The CAN filters can be configured in a different way: + * + * 1. As a match of specific IDs in a list (IdList mode), or as + * 2. And ID and a mask (IdMask mode). + * + * Filters can also be configured as: + * + * 3. 16- or 32-bit. The advantage of 16-bit filters is that you get + * more filters; The advantage of 32-bit filters is that you get + * finer control of the filtering. + * + * One filter is set up for each CAN. The filter resources are shared + * between the two CAN modules: CAN0 uses only filter 0 (but reserves + * 0 through CAN_NFILTERS/2-1); CAN1 uses only filter CAN_NFILTERS/2 + * (but reserves CAN_NFILTERS/2 through CAN_NFILTERS-1). + * + * 32-bit IdMask mode is configured. However, both the ID and the MASK + * are set to zero thus suppressing all filtering because anything masked + * with zero matches zero. + * + * Input Parameters: + * priv - A pointer to the private data structure for this CAN block + * + * Returned Value: + * Zero on success; a negated errno value on failure. + * + ****************************************************************************/ + +static int gd32can_filterinit(struct gd32_can_s *priv) +{ + uint32_t regval; + uint32_t bitmask; + + caninfo("CAN%" PRIu8 " filter: %" PRIu8 "\n", priv->port, priv->filter); + + /* Get the bitmask associated with the filter used by this CAN block */ + + bitmask = (uint32_t)1 << priv->filter; + + /* Enter filter initialization mode */ + + regval = gd32can_getfreg(priv, GD32_CAN_FMR_OFFSET); + regval |= CAN_FMR_FINIT; + gd32can_putfreg(priv, GD32_CAN_FMR_OFFSET, regval); + + /* Assign half the filters to CAN0, half to CAN1 (28 banks on GD32F4). */ + + regval = gd32can_getfreg(priv, GD32_CAN_FMR_OFFSET); + regval &= ~CAN_FMR_CAN1SB_MASK; + regval |= (CAN_NFILTERS / 2) << CAN_FMR_CAN1SB_SHIFT; + gd32can_putfreg(priv, GD32_CAN_FMR_OFFSET, regval); + + /* Disable the filter */ + + regval = gd32can_getfreg(priv, GD32_CAN_FA1R_OFFSET); + regval &= ~bitmask; + gd32can_putfreg(priv, GD32_CAN_FA1R_OFFSET, regval); + + /* Select the 32-bit scale for the filter */ + + regval = gd32can_getfreg(priv, GD32_CAN_FS1R_OFFSET); + regval |= bitmask; + gd32can_putfreg(priv, GD32_CAN_FS1R_OFFSET, regval); + + /* There are 14 or 28 filter banks (depending) on the device. + * Each filter bank is composed of two 32-bit registers, CAN_FiR: + */ + + gd32can_putfreg(priv, GD32_CAN_FIR_OFFSET(priv->filter, 1), 0); + gd32can_putfreg(priv, GD32_CAN_FIR_OFFSET(priv->filter, 2), 0); + + /* Set Id/Mask mode for the filter */ + + regval = gd32can_getfreg(priv, GD32_CAN_FM1R_OFFSET); + regval &= ~bitmask; + gd32can_putfreg(priv, GD32_CAN_FM1R_OFFSET, regval); + + /* Assign FIFO 0 for the filter */ + + regval = gd32can_getfreg(priv, GD32_CAN_FFA1R_OFFSET); + regval &= ~bitmask; + gd32can_putfreg(priv, GD32_CAN_FFA1R_OFFSET, regval); + + /* Enable the filter */ + + regval = gd32can_getfreg(priv, GD32_CAN_FA1R_OFFSET); + regval |= bitmask; + gd32can_putfreg(priv, GD32_CAN_FA1R_OFFSET, regval); + + /* Exit filter initialization mode */ + + regval = gd32can_getfreg(priv, GD32_CAN_FMR_OFFSET); + regval &= ~CAN_FMR_FINIT; + gd32can_putfreg(priv, GD32_CAN_FMR_OFFSET, regval); + return OK; +} + +/**************************************************************************** + * Name: gd32can_addextfilter + * + * Description: + * Add a filter for extended CAN IDs + * + * Input Parameters: + * priv - A pointer to the private data structure for this CAN block + * arg - A pointer to a structure describing the filter + * + * Returned Value: + * A non-negative filter ID is returned on success. + * Otherwise -1 (ERROR) is returned with the errno + * set to indicate the nature of the error. + * + ****************************************************************************/ + +#ifdef CONFIG_CAN_EXTID +static int gd32can_addextfilter(struct gd32_can_s *priv, + struct canioc_extfilter_s *arg) +{ + return -ENOTTY; +} +#endif + +/**************************************************************************** + * Name: gd32can_delextfilter + * + * Description: + * Remove a filter for extended CAN IDs + * + * Input Parameters: + * priv - A pointer to the private data structure for this CAN block + * arg - The filter index previously returned by the + * CANIOC_ADD_EXTFILTER command + * + * Returned Value: + * Zero (OK) is returned on success. Otherwise -1 (ERROR) + * returned with the errno variable set to indicate the + * of the error. + * + ****************************************************************************/ + +#ifdef CONFIG_CAN_EXTID +static int gd32can_delextfilter(struct gd32_can_s *priv, int arg) +{ + return -ENOTTY; +} +#endif + +/**************************************************************************** + * Name: gd32can_addstdfilter + * + * Description: + * Add a filter for standard CAN IDs + * + * Input Parameters: + * priv - A pointer to the private data structure for this CAN block + * arg - A pointer to a structure describing the filter + * + * Returned Value: + * A non-negative filter ID is returned on success. + * Otherwise -1 (ERROR) is returned with the errno + * set to indicate the nature of the error. + * + ****************************************************************************/ + +static int gd32can_addstdfilter(struct gd32_can_s *priv, + struct canioc_stdfilter_s *arg) +{ + return -ENOTTY; +} + +/**************************************************************************** + * Name: gd32can_delstdfilter + * + * Description: + * Remove a filter for standard CAN IDs + * + * Input Parameters: + * priv - A pointer to the private data structure for this CAN block + * arg - The filter index previously returned by the + * CANIOC_ADD_STDFILTER command + * + * Returned Value: + * Zero (OK) is returned on success. Otherwise -1 (ERROR) + * returned with the errno variable set to indicate the + * of the error. + * + ****************************************************************************/ + +static int gd32can_delstdfilter(struct gd32_can_s *priv, int arg) +{ + return -ENOTTY; +} + +/**************************************************************************** + * Name: gd32can_txmb0empty + * + * Input Parameters: + * tsr_regval - value of CAN transmit status register + * + * Returned Value: + * Returns true if mailbox 0 is empty and can be used for sending. + * + ****************************************************************************/ + +static bool gd32can_txmb0empty(uint32_t tsr_regval) +{ + return (tsr_regval & CAN_TSR_TME0) != 0 && + (tsr_regval & CAN_TSR_RQCP0) == 0; +} + +/**************************************************************************** + * Name: gd32can_txmb1empty + * + * Input Parameters: + * tsr_regval - value of CAN transmit status register + * + * Returned Value: + * Returns true if mailbox 1 is empty and can be used for sending. + * + ****************************************************************************/ + +static bool gd32can_txmb1empty(uint32_t tsr_regval) +{ + return (tsr_regval & CAN_TSR_TME1) != 0 && + (tsr_regval & CAN_TSR_RQCP1) == 0; +} + +/**************************************************************************** + * Name: gd32can_txmb2empty + * + * Input Parameters: + * tsr_regval - value of CAN transmit status register + * + * Returned Value: + * Returns true if mailbox 2 is empty and can be used for sending. + * + ****************************************************************************/ + +static bool gd32can_txmb2empty(uint32_t tsr_regval) +{ + return (tsr_regval & CAN_TSR_TME2) != 0 && + (tsr_regval & CAN_TSR_RQCP2) == 0; +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: gd32_caninitialize + * + * Description: + * Initialize the selected CAN port + * + * Input Parameters: + * Port number (for hardware that has multiple CAN interfaces) + * + * Returned Value: + * Valid CAN device structure reference on success; a NULL on failure + * + ****************************************************************************/ + +struct can_dev_s *gd32_caninitialize(int port) +{ + struct can_dev_s *dev = NULL; + + caninfo("CAN%" PRIu8 "\n", port); + + /* NOTE: Peripheral clocking for CAN is enabled here. gd32_clockconfig() + * does not currently enable CAN clocks in RCU. + */ + +#ifdef CONFIG_GD32F4_CAN0 + if (port == 0) + { + /* Select the CAN0 device structure */ + + dev = &g_can0dev; + + /* Enable CAN0 clock (filters live in CAN0 block). */ + + modifyreg32(GD32_RCU_APB1EN, 0, RCU_APB1EN_CAN0EN); + + /* Configure CAN0 pins. Ambiguous pinmap entries must be + * disambiguated in the board.h file. + */ + + gd32_gpio_config(GPIO_CAN0_RX); + gd32_gpio_config(GPIO_CAN0_TX); + } + else +#endif +#ifdef CONFIG_GD32F4_CAN1 + if (port == 1) + { + /* Select the CAN1 device structure */ + + dev = &g_can1dev; + + /* CAN1 shares filter registers with CAN0; enable both clocks. */ + + modifyreg32(GD32_RCU_APB1EN, 0, RCU_APB1EN_CAN0EN); + modifyreg32(GD32_RCU_APB1EN, 0, RCU_APB1EN_CAN1EN); + + /* Configure CAN1 pins. Ambiguous pinmap entries must be + * disambiguated in the board.h file. + */ + + gd32_gpio_config(GPIO_CAN1_RX); + gd32_gpio_config(GPIO_CAN1_TX); + } + else +#endif + { + canerr("ERROR: Unsupported port %d\n", port); + return NULL; + } + + return dev; +} + +#endif /* CONFIG_CAN && (CONFIG_GD32F4_CAN0 || CONFIG_GD32F4_CAN1) */ diff --git a/arch/arm/src/gd32f4/gd32f4xx_can.h b/arch/arm/src/gd32f4/gd32f4xx_can.h new file mode 100644 index 0000000000000..8471f55e6b1f8 --- /dev/null +++ b/arch/arm/src/gd32f4/gd32f4xx_can.h @@ -0,0 +1,136 @@ +/**************************************************************************** + * arch/arm/src/gd32f4/gd32f4xx_can.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_GD32F4_GD32F4XX_CAN_H +#define __ARCH_ARM_SRC_GD32F4_GD32F4XX_CAN_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include "chip.h" +#include "hardware/gd32f4xx_can.h" + +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +/* Up to 2 CAN interfaces are supported */ + +#if GD32_NCAN < 2 +# undef CONFIG_GD32F4_CAN1 +#endif + +#if GD32_NCAN < 1 +# undef CONFIG_GD32F4_CAN0 +#endif + +/* CAN BAUD */ + +#if defined(CONFIG_GD32F4_CAN0) && !defined(CONFIG_GD32F4_CAN0_BAUD) +# error "CONFIG_GD32F4_CAN0_BAUD is not defined" +#endif + +#if defined(CONFIG_GD32F4_CAN1) && !defined(CONFIG_GD32F4_CAN1_BAUD) +# error "CONFIG_GD32F4_CAN1_BAUD is not defined" +#endif + +/* User-defined TSEG1 and TSEG2 settings may be used. + * + * CONFIG_GD32F4_CAN_TSEG1 = the number of CAN time quanta in segment 1 + * CONFIG_GD32F4_CAN_TSEG2 = the number of CAN time quanta in segment 2 + * CAN_BIT_QUANTA = The number of CAN time quanta in one bit time + */ + +#ifndef CONFIG_GD32F4_CAN_TSEG1 +# define CONFIG_GD32F4_CAN_TSEG1 6 +#endif + +#if CONFIG_GD32F4_CAN_TSEG1 < 1 || CONFIG_GD32F4_CAN_TSEG1 > CAN_BTR_TSEG1_MAX +# error "CONFIG_GD32F4_CAN_TSEG1 is out of range" +#endif + +#ifndef CONFIG_GD32F4_CAN_TSEG2 +# define CONFIG_GD32F4_CAN_TSEG2 7 +#endif + +#if CONFIG_GD32F4_CAN_TSEG2 < 1 || CONFIG_GD32F4_CAN_TSEG2 > CAN_BTR_TSEG2_MAX +# error "CONFIG_GD32F4_CAN_TSEG2 is out of range" +#endif + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +#ifndef __ASSEMBLY__ + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +#if defined(CONFIG_GD32F4_CAN0) || defined(CONFIG_GD32F4_CAN1) + +/**************************************************************************** + * Name: gd32_caninitialize + * + * Description: + * Initialize the selected CAN port as character device + * + * Input Parameters: + * Port number (0 = CAN0, 1 = CAN1) + * + * Returned Value: + * Valid CAN device structure reference on success; a NULL on failure + * + ****************************************************************************/ + +struct can_dev_s; +struct can_dev_s *gd32_caninitialize(int port); + +#endif /* CONFIG_GD32F4_CAN0 || CONFIG_GD32F4_CAN1 */ + +#undef EXTERN +#if defined(__cplusplus) +} +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* __ARCH_ARM_SRC_GD32F4_GD32F4XX_CAN_H */ diff --git a/arch/arm/src/gd32f4/gd32f4xx_serial.c b/arch/arm/src/gd32f4/gd32f4xx_serial.c index 5ced798a320d8..52e96497b27b2 100644 --- a/arch/arm/src/gd32f4/gd32f4xx_serial.c +++ b/arch/arm/src/gd32f4/gd32f4xx_serial.c @@ -158,7 +158,6 @@ struct up_dev_s const uint8_t stop_2bits; /* True: Configure with 2 stop bits instead of 1 */ const uint32_t tx_gpio; /* USART TX GPIO pin configuration */ const uint32_t rx_gpio; /* USART RX GPIO pin configuration */ - spinlock_t lock; /* Spinlock */ # ifdef CONFIG_SERIAL_IFLOWCONTROL const uint32_t rts_gpio; /* UART RTS GPIO pin configuration */ @@ -169,6 +168,7 @@ struct up_dev_s #endif /* CONFIG_SERIAL_TERMIOS */ + spinlock_t lock; /* Spinlock */ uint32_t ie; /* USART enabled interrupts */ uint16_t sr; /* Save USART status */ @@ -467,7 +467,7 @@ static struct up_dev_s g_usart0priv = static struct uart_dev_s g_usart0port = { -#if CONSOLE_UART == 0 +#if defined(CONSOLE_UART) && CONSOLE_UART == 0 .isconsole = true, #endif .recv = @@ -540,7 +540,7 @@ static struct up_dev_s g_usart1priv = static struct uart_dev_s g_usart1port = { -#if CONSOLE_UART == 1 +#if defined(CONSOLE_UART) && CONSOLE_UART == 1 .isconsole = true, #endif .recv = @@ -613,7 +613,7 @@ static struct up_dev_s g_usart2priv = static struct uart_dev_s g_usart2port = { -#if CONSOLE_UART == 2 +#if defined(CONSOLE_UART) && CONSOLE_UART == 2 .isconsole = true, #endif .recv = @@ -686,7 +686,7 @@ static struct up_dev_s g_usart5priv = static struct uart_dev_s g_usart5port = { -#if CONSOLE_UART == 5 +#if defined(CONSOLE_UART) && CONSOLE_UART == 5 .isconsole = true, #endif .recv = @@ -759,7 +759,7 @@ static struct up_dev_s g_uart3priv = static struct uart_dev_s g_uart3port = { -#if CONSOLE_UART == 3 +#if defined(CONSOLE_UART) && CONSOLE_UART == 3 .isconsole = true, #endif .recv = @@ -832,7 +832,7 @@ static struct up_dev_s g_uart4priv = static struct uart_dev_s g_uart4port = { -#if CONSOLE_UART == 3 +#if defined(CONSOLE_UART) && CONSOLE_UART == 4 .isconsole = true, #endif .recv = @@ -905,7 +905,7 @@ static struct up_dev_s g_uart6priv = static struct uart_dev_s g_uart6port = { -#if CONSOLE_UART == 3 +#if defined(CONSOLE_UART) && CONSOLE_UART == 6 .isconsole = true, #endif .recv = @@ -978,7 +978,7 @@ static struct up_dev_s g_uart7priv = static struct uart_dev_s g_uart7port = { -#if CONSOLE_UART == 3 +#if defined(CONSOLE_UART) && CONSOLE_UART == 7 .isconsole = true, #endif .recv = @@ -2793,7 +2793,9 @@ void arm_earlyserialinit(void) /* Configure whichever one is the console */ +#ifdef CONSOLE_UART up_setup(g_uart_devs[CONSOLE_UART]); +#endif #endif /* HAVE UART */ } #endif diff --git a/arch/arm/src/gd32f4/hardware/gd32f450_memorymap.h b/arch/arm/src/gd32f4/hardware/gd32f450_memorymap.h index 5a263a29c913e..139d307fc3f5a 100644 --- a/arch/arm/src/gd32f4/hardware/gd32f450_memorymap.h +++ b/arch/arm/src/gd32f4/hardware/gd32f450_memorymap.h @@ -101,7 +101,9 @@ #define GD32_SPI_BASE (GD32_APB1_BUS_BASE + 0x00003800U) /* SPI base address */ #define GD32_USART_BASE (GD32_APB1_BUS_BASE + 0x00004400U) /* USART base address */ #define GD32_I2C_BASE (GD32_APB1_BUS_BASE + 0x00005400U) /* I2C base address */ -#define GD32_CAN_BASE (GD32_APB1_BUS_BASE + 0x00006400U) /* CAN base address */ +#define GD32_CAN0_BASE (GD32_APB1_BUS_BASE + 0x00006400U) /* CAN0 base address */ +#define GD32_CAN1_BASE (GD32_APB1_BUS_BASE + 0x00006800U) /* CAN1 base address */ +#define GD32_CAN_BASE GD32_CAN0_BASE /* Alias: CAN0 */ #define GD32_CTC_BASE (GD32_APB1_BUS_BASE + 0x00006C00U) /* CTC base address */ #define GD32_PMU_BASE (GD32_APB1_BUS_BASE + 0x00007000U) /* PMU base address */ #define GD32_DAC_BASE (GD32_APB1_BUS_BASE + 0x00007400U) /* DAC base address */ diff --git a/arch/arm/src/gd32f4/hardware/gd32f4xx_can.h b/arch/arm/src/gd32f4/hardware/gd32f4xx_can.h new file mode 100644 index 0000000000000..5a22e30b8a958 --- /dev/null +++ b/arch/arm/src/gd32f4/hardware/gd32f4xx_can.h @@ -0,0 +1,470 @@ +/**************************************************************************** + * arch/arm/src/gd32f4/hardware/gd32f4xx_can.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_GD32F4_HARDWARE_GD32F4XX_CAN_H +#define __ARCH_ARM_SRC_GD32F4_HARDWARE_GD32F4XX_CAN_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include "chip.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* 3 TX mailboxes */ + +#define CAN_TXMBOX1 0 +#define CAN_TXMBOX2 1 +#define CAN_TXMBOX3 2 + +/* 2 RX mailboxes */ + +#define CAN_RXMBOX1 0 +#define CAN_RXMBOX2 1 + +/* GD32F4 bxCAN has 28 filter banks (shared by CAN0/CAN1) */ + +#define CAN_NFILTERS 28 + +/* Register Offsets *********************************************************/ + +/* CAN control and status registers */ + +#define GD32_CAN_MCR_OFFSET 0x0000 /* CAN master control register */ +#define GD32_CAN_MSR_OFFSET 0x0004 /* CAN master status register */ +#define GD32_CAN_TSR_OFFSET 0x0008 /* CAN transmit status register */ + +#define GD32_CAN_RFR_OFFSET(m) (0x000c+((m)<<2)) +#define GD32_CAN_RF0R_OFFSET 0x000c /* CAN receive FIFO 0 register */ +#define GD32_CAN_RF1R_OFFSET 0x0010 /* CAN receive FIFO 1 register */ + +#define GD32_CAN_IER_OFFSET 0x0014 /* CAN interrupt enable register */ +#define GD32_CAN_ESR_OFFSET 0x0018 /* CAN error status register */ +#define GD32_CAN_BTR_OFFSET 0x001c /* CAN bit timing register */ + +/* CAN mailbox registers (3 TX and 2 RX) */ + +#define GD32_CAN_TIR_OFFSET(m) (0x0180+((m)<<4)) +#define GD32_CAN_TI0R_OFFSET 0x0180 /* TX mailbox identifier register 0 */ +#define GD32_CAN_TI1R_OFFSET 0x0190 /* TX mailbox identifier register 1 */ +#define GD32_CAN_TI2R_OFFSET 0x01a0 /* TX mailbox identifier register 2 */ + +#define GD32_CAN_TDTR_OFFSET(m) (0x0184+((m)<<4)) +#define GD32_CAN_TDT0R_OFFSET 0x0184 /* Mailbox data length control and time stamp register 0 */ +#define GD32_CAN_TDT1R_OFFSET 0x0194 /* Mailbox data length control and time stamp register 1 */ +#define GD32_CAN_TDT2R_OFFSET 0x01a4 /* Mailbox data length control and time stamp register 2 */ + +#define GD32_CAN_TDLR_OFFSET(m) (0x0188+((m)<<4)) +#define GD32_CAN_TDL0R_OFFSET 0x0188 /* Mailbox data low register 0 */ +#define GD32_CAN_TDL1R_OFFSET 0x0198 /* Mailbox data low register 1 */ +#define GD32_CAN_TDL2R_OFFSET 0x01a8 /* Mailbox data low register 2 */ + +#define GD32_CAN_TDHR_OFFSET(m) (0x018c+((m)<<4)) +#define GD32_CAN_TDH0R_OFFSET 0x018c /* Mailbox data high register 0 */ +#define GD32_CAN_TDH1R_OFFSET 0x019c /* Mailbox data high register 1 */ +#define GD32_CAN_TDH2R_OFFSET 0x01ac /* Mailbox data high register 2 */ + +#define GD32_CAN_RIR_OFFSET(m) (0x01b0+((m)<<4)) +#define GD32_CAN_RI0R_OFFSET 0x01b0 /* Rx FIFO mailbox identifier register 0 */ +#define GD32_CAN_RI1R_OFFSET 0x01c0 /* Rx FIFO mailbox identifier register 1 */ + +#define GD32_CAN_RDTR_OFFSET(m) (0x01b4+((m)<<4)) +#define GD32_CAN_RDT0R_OFFSET 0x01b4 /* Rx FIFO mailbox data length control and time stamp register 0 */ +#define GD32_CAN_RDT1R_OFFSET 0x01c4 /* Rx FIFO mailbox data length control and time stamp register 1 */ + +#define GD32_CAN_RDLR_OFFSET(m) (0x01b8+((m)<<4)) +#define GD32_CAN_RDL0R_OFFSET 0x01b8 /* Receive FIFO mailbox data low register 0 */ +#define GD32_CAN_RDL1R_OFFSET 0x01c8 /* Receive FIFO mailbox data low register 1 */ + +#define GD32_CAN_RDHR_OFFSET(m) (0x01bc+((m)<<4)) +#define GD32_CAN_RDH0R_OFFSET 0x01bc /* Receive FIFO mailbox data high register 0 */ +#define GD32_CAN_RDH1R_OFFSET 0x01cc /* Receive FIFO mailbox data high register 1 */ + +/* CAN filter registers */ + +#define GD32_CAN_FMR_OFFSET 0x0200 /* CAN filter master register */ +#define GD32_CAN_FM1R_OFFSET 0x0204 /* CAN filter mode register */ +#define GD32_CAN_FS1R_OFFSET 0x020c /* CAN filter scale register */ +#define GD32_CAN_FFA1R_OFFSET 0x0214 /* CAN filter FIFO assignment register */ +#define GD32_CAN_FA1R_OFFSET 0x021c /* CAN filter activation register */ + +/* There are 14 or 28 filter banks (depending) on the device. + * Each filter bank is composed of two 32-bit registers, CAN_FiR: + * F0R1 Offset 0x240 + * F0R2 Offset 0x244 + * F1R1 Offset 0x248 + * F1R2 Offset 0x24c + * ... + */ + +#define GD32_CAN_FIR_OFFSET(f,i) (0x240+((f)<<3)+(((i)-1)<<2)) + +/* Register Addresses *******************************************************/ + +#if GD32_NCAN > 0 +# define GD32_CAN0_MCR (GD32_CAN0_BASE+GD32_CAN_MCR_OFFSET) +# define GD32_CAN0_MSR (GD32_CAN0_BASE+GD32_CAN_MSR_OFFSET) +# define GD32_CAN0_TSR (GD32_CAN0_BASE+GD32_CAN_TSR_OFFSET) +# define GD32_CAN0_RF0R (GD32_CAN0_BASE+GD32_CAN_RF0R_OFFSET) +# define GD32_CAN0_RF1R (GD32_CAN0_BASE+GD32_CAN_RF1R_OFFSET) +# define GD32_CAN0_IER (GD32_CAN0_BASE+GD32_CAN_IER_OFFSET) +# define GD32_CAN0_ESR (GD32_CAN0_BASE+GD32_CAN_ESR_OFFSET) +# define GD32_CAN0_BTR (GD32_CAN0_BASE+GD32_CAN_BTR_OFFSET) + +# define GD32_CAN0_TIR(m) (GD32_CAN0_BASE+GD32_CAN_TIR_OFFSET(m)) +# define GD32_CAN0_TI0R (GD32_CAN0_BASE+GD32_CAN_TI0R_OFFSET) +# define GD32_CAN0_TI1R (GD32_CAN0_BASE+GD32_CAN_TI1R_OFFSET) +# define GD32_CAN0_TI2R (GD32_CAN0_BASE+GD32_CAN_TI2R_OFFSET) + +# define GD32_CAN0_TDTR(m) (GD32_CAN0_BASE+GD32_CAN_TDTR_OFFSET(m)) +# define GD32_CAN0_TDT0R (GD32_CAN0_BASE+GD32_CAN_TDT0R_OFFSET) +# define GD32_CAN0_TDT1R (GD32_CAN0_BASE+GD32_CAN_TDT1R_OFFSET) +# define GD32_CAN0_TDT2R (GD32_CAN0_BASE+GD32_CAN_TDT2R_OFFSET) + +# define GD32_CAN0_TDLR(m) (GD32_CAN0_BASE+GD32_CAN_TDLR_OFFSET(m)) +# define GD32_CAN0_TDL0R (GD32_CAN0_BASE+GD32_CAN_TDL0R_OFFSET) +# define GD32_CAN0_TDL1R (GD32_CAN0_BASE+GD32_CAN_TDL1R_OFFSET) +# define GD32_CAN0_TDL2R (GD32_CAN0_BASE+GD32_CAN_TDL2R_OFFSET) + +# define GD32_CAN0_TDHR(m) (GD32_CAN0_BASE+GD32_CAN_TDHR_OFFSET(m)) +# define GD32_CAN0_TDH0R (GD32_CAN0_BASE+GD32_CAN_TDH0R_OFFSET) +# define GD32_CAN0_TDH1R (GD32_CAN0_BASE+GD32_CAN_TDH1R_OFFSET) +# define GD32_CAN0_TDH2R (GD32_CAN0_BASE+GD32_CAN_TDH2R_OFFSET) + +# define GD32_CAN0_RIR(m) (GD32_CAN0_BASE+GD32_CAN_RIR_OFFSET(m)) +# define GD32_CAN0_RI0R (GD32_CAN0_BASE+GD32_CAN_RI0R_OFFSET) +# define GD32_CAN0_RI1R (GD32_CAN0_BASE+GD32_CAN_RI1R_OFFSET) + +# define GD32_CAN0_RDTR(m) (GD32_CAN0_BASE+GD32_CAN_RDTR_OFFSET(m)) +# define GD32_CAN0_RDT0R (GD32_CAN0_BASE+GD32_CAN_RDT0R_OFFSET) +# define GD32_CAN0_RDT1R (GD32_CAN0_BASE+GD32_CAN_RDT1R_OFFSET) + +# define GD32_CAN0_RDLR(m) (GD32_CAN0_BASE+GD32_CAN_RDLR_OFFSET(m)) +# define GD32_CAN0_RDL0R (GD32_CAN0_BASE+GD32_CAN_RDL0R_OFFSET) +# define GD32_CAN0_RDL1R (GD32_CAN0_BASE+GD32_CAN_RDL1R_OFFSET) + +# define GD32_CAN0_RDHR(m) (GD32_CAN0_BASE+GD32_CAN_RDHR_OFFSET(m)) +# define GD32_CAN0_RDH0R (GD32_CAN0_BASE+GD32_CAN_RDH0R_OFFSET) +# define GD32_CAN0_RDH1R (GD32_CAN0_BASE+GD32_CAN_RDH1R_OFFSET) + +# define GD32_CAN0_FMR (GD32_CAN0_BASE+GD32_CAN_FMR_OFFSET) +# define GD32_CAN0_FM1R (GD32_CAN0_BASE+GD32_CAN_FM1R_OFFSET) +# define GD32_CAN0_FS1R (GD32_CAN0_BASE+GD32_CAN_FS1R_OFFSET) +# define GD32_CAN0_FFA1R (GD32_CAN0_BASE+GD32_CAN_FFA1R_OFFSET) +# define GD32_CAN0_FA1R (GD32_CAN0_BASE+GD32_CAN_FA1R_OFFSET) +# define GD32_CAN0_FIR(b,i) (GD32_CAN0_BASE+GD32_CAN_FIR_OFFSET(b,i)) +#endif + +#if GD32_NCAN > 1 +# define GD32_CAN1_MCR (GD32_CAN1_BASE+GD32_CAN_MCR_OFFSET) +# define GD32_CAN1_MSR (GD32_CAN1_BASE+GD32_CAN_MSR_OFFSET) +# define GD32_CAN1_TSR (GD32_CAN1_BASE+GD32_CAN_TSR_OFFSET) +# define GD32_CAN1_RF0R (GD32_CAN1_BASE+GD32_CAN_RF0R_OFFSET) +# define GD32_CAN1_RF1R (GD32_CAN1_BASE+GD32_CAN_RF1R_OFFSET) +# define GD32_CAN1_IER (GD32_CAN1_BASE+GD32_CAN_IER_OFFSET) +# define GD32_CAN1_ESR (GD32_CAN1_BASE+GD32_CAN_ESR_OFFSET) +# define GD32_CAN1_BTR (GD32_CAN1_BASE+GD32_CAN_BTR_OFFSET) + +# define GD32_CAN1_TIR(m) (GD32_CAN1_BASE+GD32_CAN_TIR_OFFSET(m)) +# define GD32_CAN1_TI0R (GD32_CAN1_BASE+GD32_CAN_TI0R_OFFSET) +# define GD32_CAN1_TI1R (GD32_CAN1_BASE+GD32_CAN_TI1R_OFFSET) +# define GD32_CAN1_TI2R (GD32_CAN1_BASE+GD32_CAN_TI2R_OFFSET) + +# define GD32_CAN1_TDTR(m) (GD32_CAN1_BASE+GD32_CAN_TDTR_OFFSET(m)) +# define GD32_CAN1_TDT0R (GD32_CAN1_BASE+GD32_CAN_TDT0R_OFFSET) +# define GD32_CAN1_TDT1R (GD32_CAN1_BASE+GD32_CAN_TDT1R_OFFSET) +# define GD32_CAN1_TDT2R (GD32_CAN1_BASE+GD32_CAN_TDT2R_OFFSET) + +# define GD32_CAN1_TDLR(m) (GD32_CAN1_BASE+GD32_CAN_TDLR_OFFSET(m)) +# define GD32_CAN1_TDL0R (GD32_CAN1_BASE+GD32_CAN_TDL0R_OFFSET) +# define GD32_CAN1_TDL1R (GD32_CAN1_BASE+GD32_CAN_TDL1R_OFFSET) +# define GD32_CAN1_TDL2R (GD32_CAN1_BASE+GD32_CAN_TDL2R_OFFSET) + +# define GD32_CAN1_TDHR(m) (GD32_CAN1_BASE+GD32_CAN_TDHR_OFFSET(m)) +# define GD32_CAN1_TDH0R (GD32_CAN1_BASE+GD32_CAN_TDH0R_OFFSET) +# define GD32_CAN1_TDH1R (GD32_CAN1_BASE+GD32_CAN_TDH1R_OFFSET) +# define GD32_CAN1_TDH2R (GD32_CAN1_BASE+GD32_CAN_TDH2R_OFFSET) + +# define GD32_CAN1_RIR(m) (GD32_CAN1_BASE+GD32_CAN_RIR_OFFSET(m)) +# define GD32_CAN1_RI0R (GD32_CAN1_BASE+GD32_CAN_RI0R_OFFSET) +# define GD32_CAN1_RI1R (GD32_CAN1_BASE+GD32_CAN_RI1R_OFFSET) + +# define GD32_CAN1_RDTR(m) (GD32_CAN1_BASE+GD32_CAN_RDTR_OFFSET(m)) +# define GD32_CAN1_RDT0R (GD32_CAN1_BASE+GD32_CAN_RDT0R_OFFSET) +# define GD32_CAN1_RDT1R (GD32_CAN1_BASE+GD32_CAN_RDT1R_OFFSET) + +# define GD32_CAN1_RDLR(m) (GD32_CAN1_BASE+GD32_CAN_RDLR_OFFSET(m)) +# define GD32_CAN1_RDL0R (GD32_CAN1_BASE+GD32_CAN_RDL0R_OFFSET) +# define GD32_CAN1_RDL1R (GD32_CAN1_BASE+GD32_CAN_RDL1R_OFFSET) + +# define GD32_CAN1_RDHR(m) (GD32_CAN1_BASE+GD32_CAN_RDHR_OFFSET(m)) +# define GD32_CAN1_RDH0R (GD32_CAN1_BASE+GD32_CAN_RDH0R_OFFSET) +# define GD32_CAN1_RDH1R (GD32_CAN1_BASE+GD32_CAN_RDH1R_OFFSET) + +# define GD32_CAN1_FMR (GD32_CAN1_BASE+GD32_CAN_FMR_OFFSET) +# define GD32_CAN1_FM1R (GD32_CAN1_BASE+GD32_CAN_FM1R_OFFSET) +# define GD32_CAN1_FS1R (GD32_CAN1_BASE+GD32_CAN_FS1R_OFFSET) +# define GD32_CAN1_FFA1R (GD32_CAN1_BASE+GD32_CAN_FFA1R_OFFSET) +# define GD32_CAN1_FA1R (GD32_CAN1_BASE+GD32_CAN_FA1R_OFFSET) +# define GD32_CAN1_FIR(b,i) (GD32_CAN1_BASE+GD32_CAN_FIR_OFFSET(b,i)) +#endif + +/* Register Bitfield Definitions ********************************************/ + +/* CAN master control register */ + +#define CAN_MCR_INRQ (1 << 0) /* Bit 0: Initialization Request */ +#define CAN_MCR_SLEEP (1 << 1) /* Bit 1: Sleep Mode Request */ +#define CAN_MCR_TXFP (1 << 2) /* Bit 2: Transmit FIFO Priority */ +#define CAN_MCR_RFLM (1 << 3) /* Bit 3: Receive FIFO Locked Mode */ +#define CAN_MCR_NART (1 << 4) /* Bit 4: No Automatic Retransmission */ +#define CAN_MCR_AWUM (1 << 5) /* Bit 5: Automatic Wakeup Mode */ +#define CAN_MCR_ABOM (1 << 6) /* Bit 6: Automatic Bus-Off Management */ +#define CAN_MCR_TTCM (1 << 7) /* Bit 7: Time Triggered Communication Mode Enable */ +#define CAN_MCR_RESET (1 << 15) /* Bit 15: bxCAN software master reset */ +#define CAN_MCR_DBF (1 << 16) /* Bit 16: Debug freeze */ + +/* CAN master status register */ + +#define CAN_MSR_INAK (1 << 0) /* Bit 0: Initialization Acknowledge */ +#define CAN_MSR_SLAK (1 << 1) /* Bit 1: Sleep Acknowledge */ +#define CAN_MSR_ERRI (1 << 2) /* Bit 2: Error Interrupt */ +#define CAN_MSR_WKUI (1 << 3) /* Bit 3: Wakeup Interrupt */ +#define CAN_MSR_SLAKI (1 << 4) /* Bit 4: Sleep acknowledge interrupt */ +#define CAN_MSR_TXM (1 << 8) /* Bit 8: Transmit Mode */ +#define CAN_MSR_RXM (1 << 9) /* Bit 9: Receive Mode */ +#define CAN_MSR_SAMP (1 << 10) /* Bit 10: Last Sample Point */ +#define CAN_MSR_RX (1 << 11) /* Bit 11: CAN Rx Signal */ + +/* CAN transmit status register */ + +#define CAN_TSR_RQCP0 (1 << 0) /* Bit 0: Request Completed Mailbox 0 */ +#define CAN_TSR_TXOK0 (1 << 1) /* Bit 1 : Transmission OK of Mailbox 0 */ +#define CAN_TSR_ALST0 (1 << 2) /* Bit 2 : Arbitration Lost for Mailbox 0 */ +#define CAN_TSR_TERR0 (1 << 3) /* Bit 3 : Transmission Error of Mailbox 0 */ +#define CAN_TSR_ABRQ0 (1 << 7) /* Bit 7 : Abort Request for Mailbox 0 */ +#define CAN_TSR_RQCP1 (1 << 8) /* Bit 8 : Request Completed Mailbox 1 */ +#define CAN_TSR_TXOK1 (1 << 9) /* Bit 9 : Transmission OK of Mailbox 1 */ +#define CAN_TSR_ALST1 (1 << 10) /* Bit 10 : Arbitration Lost for Mailbox 1 */ +#define CAN_TSR_TERR1 (1 << 11) /* Bit 11 : Transmission Error of Mailbox 1 */ +#define CAN_TSR_ABRQ1 (1 << 15) /* Bit 15 : Abort Request for Mailbox 1 */ +#define CAN_TSR_RQCP2 (1 << 16) /* Bit 16 : Request Completed Mailbox 2 */ +#define CAN_TSR_TXOK2 (1 << 17) /* Bit 17 : Transmission OK of Mailbox 2 */ +#define CAN_TSR_ALST2 (1 << 18) /* Bit 18: Arbitration Lost for Mailbox 2 */ +#define CAN_TSR_TERR2 (1 << 19) /* Bit 19: Transmission Error of Mailbox 2 */ +#define CAN_TSR_ABRQ2 (1 << 23) /* Bit 23: Abort Request for Mailbox 2 */ +#define CAN_TSR_CODE_SHIFT (24) /* Bits 25-24: Mailbox Code */ +#define CAN_TSR_CODE_MASK (3 << CAN_TSR_CODE_SHIFT) +#define CAN_TSR_TME0 (1 << 26) /* Bit 26: Transmit Mailbox 0 Empty */ +#define CAN_TSR_TME1 (1 << 27) /* Bit 27: Transmit Mailbox 1 Empty */ +#define CAN_TSR_TME2 (1 << 28) /* Bit 28: Transmit Mailbox 2 Empty */ +#define CAN_TSR_LOW0 (1 << 29) /* Bit 29: Lowest Priority Flag for Mailbox 0 */ +#define CAN_TSR_LOW1 (1 << 30) /* Bit 30: Lowest Priority Flag for Mailbox 1 */ +#define CAN_TSR_LOW2 (1 << 31) /* Bit 31: Lowest Priority Flag for Mailbox 2 */ + +/* CAN receive FIFO 0/1 registers */ + +#define CAN_RFR_FMP_SHIFT (0) /* Bits 1-0: FIFO Message Pending */ +#define CAN_RFR_FMP_MASK (3 << CAN_RFR_FMP_SHIFT) +#define CAN_RFR_FULL (1 << 3) /* Bit 3: FIFO 0 Full */ +#define CAN_RFR_FOVR (1 << 4) /* Bit 4: FIFO 0 Overrun */ +#define CAN_RFR_RFOM (1 << 5) /* Bit 5: Release FIFO 0 Output Mailbox */ + +/* CAN interrupt enable register */ + +#define CAN_IER_TMEIE (1 << 0) /* Bit 0: Transmit Mailbox Empty Interrupt Enable */ +#define CAN_IER_FMPIE0 (1 << 1) /* Bit 1: FIFO Message Pending Interrupt Enable */ +#define CAN_IER_FFIE0 (1 << 2) /* Bit 2: FIFO Full Interrupt Enable */ +#define CAN_IER_FOVIE0 (1 << 3) /* Bit 3: FIFO Overrun Interrupt Enable */ +#define CAN_IER_FMPIE1 (1 << 4) /* Bit 4: FIFO Message Pending Interrupt Enable */ +#define CAN_IER_FFIE1 (1 << 5) /* Bit 5: FIFO Full Interrupt Enable */ +#define CAN_IER_FOVIE1 (1 << 6) /* Bit 6: FIFO Overrun Interrupt Enable */ +#define CAN_IER_EWGIE (1 << 8) /* Bit 8: Error Warning Interrupt Enable */ +#define CAN_IER_EPVIE (1 << 9) /* Bit 9: Error Passive Interrupt Enable */ +#define CAN_IER_BOFIE (1 << 10) /* Bit 10: Bus-Off Interrupt Enable */ +#define CAN_IER_LECIE (1 << 11) /* Bit 11: Last Error Code Interrupt Enable */ +#define CAN_IER_ERRIE (1 << 15) /* Bit 15: Error Interrupt Enable */ +#define CAN_IER_WKUIE (1 << 16) /* Bit 16: Wakeup Interrupt Enable */ +#define CAN_IER_SLKIE (1 << 17) /* Bit 17: Sleep Interrupt Enable */ + +/* CAN error status register */ + +#define CAN_ESR_EWGF (1 << 0) /* Bit 0: Error Warning Flag */ +#define CAN_ESR_EPVF (1 << 1) /* Bit 1: Error Passive Flag */ +#define CAN_ESR_BOFF (1 << 2) /* Bit 2: Bus-Off Flag */ +#define CAN_ESR_LEC_SHIFT (4) /* Bits 6-4: Last Error Code */ +#define CAN_ESR_LEC_MASK (7 << CAN_ESR_LEC_SHIFT) +# define CAN_ESR_NOERROR (0 << CAN_ESR_LEC_SHIFT) /* 000: No Error */ +# define CAN_ESR_STUFFERROR (1 << CAN_ESR_LEC_SHIFT) /* 001: Stuff Error */ +# define CAN_ESR_FORMERROR (2 << CAN_ESR_LEC_SHIFT) /* 010: Form Error */ +# define CAN_ESR_ACKERROR (3 << CAN_ESR_LEC_SHIFT) /* 011: Acknowledgment Error */ +# define CAN_ESR_BRECERROR (4 << CAN_ESR_LEC_SHIFT) /* 100: Bit recessive Error */ +# define CAN_ESR_BDOMERROR (5 << CAN_ESR_LEC_SHIFT) /* 101: Bit dominant Error */ +# define CAN_ESR_CRCERRPR (6 << CAN_ESR_LEC_SHIFT) /* 110: CRC Error */ +# define CAN_ESR_SWERROR (7 << CAN_ESR_LEC_SHIFT) /* 111: Set by software */ + +#define CAN_ESR_TEC_SHIFT (16) /* Bits 23-16: LS byte of the 9-bit Transmit Error Counter */ +#define CAN_ESR_TEC_MASK (0xff << CAN_ESR_TEC_SHIFT) +#define CAN_ESR_REC_SHIFT (24) /* Bits 31-24: Receive Error Counter */ +#define CAN_ESR_REC_MASK (0xff << CAN_ESR_REC_SHIFT) + +/* CAN bit timing register */ + +#define CAN_BTR_BRP_SHIFT (0) /* Bits 9-0: Baud Rate Prescaler */ +#define CAN_BTR_BRP_MASK (0x03ff << CAN_BTR_BRP_SHIFT) +#define CAN_BTR_TS1_SHIFT (16) /* Bits 19-16: Time Segment 1 */ +#define CAN_BTR_TS1_MASK (0x0f << CAN_BTR_TS1_SHIFT) +#define CAN_BTR_TS2_SHIFT (20) /* Bits 22-20: Time Segment 2 */ +#define CAN_BTR_TS2_MASK (7 << CAN_BTR_TS2_SHIFT) +#define CAN_BTR_SJW_SHIFT (24) /* Bits 25-24: Resynchronization Jump Width */ +#define CAN_BTR_SJW_MASK (3 << CAN_BTR_SJW_SHIFT) +#define CAN_BTR_LBKM (1 << 30) /* Bit 30: Loop Back Mode (Debug) */ +#define CAN_BTR_SILM (1ul << 31) /* Bit 31: Silent Mode (Debug) */ + +#define CAN_BTR_BRP_MAX (1024) /* Maximum BTR value (without decrement) */ +#define CAN_BTR_TSEG1_MAX (16) /* Maximum TSEG1 value (without decrement) */ +#define CAN_BTR_TSEG2_MAX (8) /* Maximum TSEG2 value (without decrement) */ + +/* TX mailbox identifier register */ + +#define CAN_TIR_TXRQ (1 << 0) /* Bit 0: Transmit Mailbox Request */ +#define CAN_TIR_RTR (1 << 1) /* Bit 1: Remote Transmission Request */ +#define CAN_TIR_IDE (1 << 2) /* Bit 2: Identifier Extension */ +#define CAN_TIR_EXID_SHIFT (3) /* Bit 3-31: Extended Identifier */ +#define CAN_TIR_EXID_MASK (0x1fffffff << CAN_TIR_EXID_SHIFT) +#define CAN_TIR_STID_SHIFT (21) /* Bits 21-31: Standard Identifier */ +#define CAN_TIR_STID_MASK (0x07ff << CAN_TIR_STID_SHIFT) + +/* Mailbox data length control and time stamp register */ + +#define CAN_TDTR_DLC_SHIFT (0) /* Bits 3:0: Data Length Code */ +#define CAN_TDTR_DLC_MASK (0x0f << CAN_TDTR_DLC_SHIFT) +#define CAN_TDTR_TGT (1 << 8) /* Bit 8: Transmit Global Time */ +#define CAN_TDTR_TIME_SHIFT (16) /* Bits 31:16: Message Time Stamp */ +#define CAN_TDTR_TIME_MASK (0xffff << CAN_TDTR_TIME_SHIFT) + +/* Mailbox data low register */ + +#define CAN_TDLR_DATA0_SHIFT (0) /* Bits 7-0: Data Byte 0 */ +#define CAN_TDLR_DATA0_MASK (0xff << CAN_TDLR_DATA0_SHIFT) +#define CAN_TDLR_DATA1_SHIFT (8) /* Bits 15-8: Data Byte 1 */ +#define CAN_TDLR_DATA1_MASK (0xff << CAN_TDLR_DATA1_SHIFT) +#define CAN_TDLR_DATA2_SHIFT (16) /* Bits 23-16: Data Byte 2 */ +#define CAN_TDLR_DATA2_MASK (0xff << CAN_TDLR_DATA2_SHIFT) +#define CAN_TDLR_DATA3_SHIFT (24) /* Bits 31-24: Data Byte 3 */ +#define CAN_TDLR_DATA3_MASK (0xff << CAN_TDLR_DATA3_SHIFT) + +/* Mailbox data high register */ + +#define CAN_TDHR_DATA4_SHIFT (0) /* Bits 7-0: Data Byte 4 */ +#define CAN_TDHR_DATA4_MASK (0xff << CAN_TDHR_DATA4_SHIFT) +#define CAN_TDHR_DATA5_SHIFT (8) /* Bits 15-8: Data Byte 5 */ +#define CAN_TDHR_DATA5_MASK (0xff << CAN_TDHR_DATA5_SHIFT) +#define CAN_TDHR_DATA6_SHIFT (16) /* Bits 23-16: Data Byte 6 */ +#define CAN_TDHR_DATA6_MASK (0xff << CAN_TDHR_DATA6_SHIFT) +#define CAN_TDHR_DATA7_SHIFT (24) /* Bits 31-24: Data Byte 7 */ +#define CAN_TDHR_DATA7_MASK (0xff << CAN_TDHR_DATA7_SHIFT) + +/* Rx FIFO mailbox identifier register */ + +#define CAN_RIR_RTR (1 << 1) /* Bit 1: Remote Transmission Request */ +#define CAN_RIR_IDE (1 << 2) /* Bit 2: Identifier Extension */ +#define CAN_RIR_EXID_SHIFT (3) /* Bit 3-31: Extended Identifier */ +#define CAN_RIR_EXID_MASK (0x1fffffff << CAN_RIR_EXID_SHIFT) +#define CAN_RIR_STID_SHIFT (21) /* Bits 21-31: Standard Identifier */ +#define CAN_RIR_STID_MASK (0x07ff << CAN_RIR_STID_SHIFT) + +/* Receive FIFO mailbox data length control and time stamp register */ + +#define CAN_RDTR_DLC_SHIFT (0) /* Bits 3:0: Data Length Code */ +#define CAN_RDTR_DLC_MASK (0x0f << CAN_RDTR_DLC_SHIFT) +#define CAN_RDTR_FM_SHIFT (8) /* Bits 15-8: Filter Match Index */ +#define CAN_RDTR_FM_MASK (0xff << CAN_RDTR_FM_SHIFT) +#define CAN_RDTR_TIME_SHIFT (16) /* Bits 31:16: Message Time Stamp */ +#define CAN_RDTR_TIME_MASK (0xffff << CAN_RDTR_TIME_SHIFT) + +/* Receive FIFO mailbox data low register */ + +#define CAN_RDLR_DATA0_SHIFT (0) /* Bits 7-0: Data Byte 0 */ +#define CAN_RDLR_DATA0_MASK (0xff << CAN_RDLR_DATA0_SHIFT) +#define CAN_RDLR_DATA1_SHIFT (8) /* Bits 15-8: Data Byte 1 */ +#define CAN_RDLR_DATA1_MASK (0xff << CAN_RDLR_DATA1_SHIFT) +#define CAN_RDLR_DATA2_SHIFT (16) /* Bits 23-16: Data Byte 2 */ +#define CAN_RDLR_DATA2_MASK (0xff << CAN_RDLR_DATA2_SHIFT) +#define CAN_RDLR_DATA3_SHIFT (24) /* Bits 31-24: Data Byte 3 */ +#define CAN_RDLR_DATA3_MASK (0xff << CAN_RDLR_DATA3_SHIFT) + +/* Receive FIFO mailbox data high register */ + +#define CAN_RDHR_DATA4_SHIFT (0) /* Bits 7-0: Data Byte 4 */ +#define CAN_RDHR_DATA4_MASK (0xff << CAN_RDHR_DATA4_SHIFT) +#define CAN_RDHR_DATA5_SHIFT (8) /* Bits 15-8: Data Byte 5 */ +#define CAN_RDHR_DATA5_MASK (0xff << CAN_RDHR_DATA5_SHIFT) +#define CAN_RDHR_DATA6_SHIFT (16) /* Bits 23-16: Data Byte 6 */ +#define CAN_RDHR_DATA6_MASK (0xff << CAN_RDHR_DATA6_SHIFT) +#define CAN_RDHR_DATA7_SHIFT (24) /* Bits 31-24: Data Byte 7 */ +#define CAN_RDHR_DATA7_MASK (0xff << CAN_RDHR_DATA7_SHIFT) + +/* CAN filter master register */ + +#define CAN_FMR_FINIT (1 << 0) /* Bit 0: Filter Init Mode */ +#define CAN_FMR_CAN1SB_SHIFT (8) /* Bits 13-8: CAN1 start bank */ +#define CAN_FMR_CAN1SB_MASK (0x3f << CAN_FMR_CAN1SB_SHIFT) + +/* CAN filter mode register */ + +#define CAN_FM1R_FBM_SHIFT (0) /* Bits 27:0: Filter Mode */ +#define CAN_FM1R_FBM_MASK (0x0fffffff << CAN_FM1R_FBM_SHIFT) + +/* CAN filter scale register */ + +#define CAN_FS1R_FSC_SHIFT (0) /* Bits 27:0: Filter Scale Configuration */ +#define CAN_FS1R_FSC_MASK (0x0fffffff << CAN_FS1R_FSC_SHIFT) + +/* CAN filter FIFO assignment register */ + +#define CAN_FFA1R_FFA_SHIFT (0) /* Bits 27:0: Filter FIFO Assignment */ +#define CAN_FFA1R_FFA_MASK (0x0fffffff << CAN_FFA1R_FFA_SHIFT) + +/* CAN filter activation register */ + +#define CAN_FA1R_FACT_SHIFT (0) /* Bits 27:0: Filter Active */ +#define CAN_FA1R_FACT_MASK (0x0fffffff << CAN_FA1R_FACT_SHIFT) + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ + +#endif /* __ARCH_ARM_SRC_GD32F4_HARDWARE_GD32F4XX_CAN_H */