From 2e6bc0995e41482979e60c1acf0602ee05bcfc1a Mon Sep 17 00:00:00 2001 From: daijoubu Date: Wed, 27 May 2026 19:41:01 -0700 Subject: [PATCH 1/2] fix: make PLL2M dynamic to keep VCO=800MHz for any HSE frequency MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit PLL2M was hardcoded to 5, which assumes HSE = 8 MHz (giving VCO = 800 MHz). On KakuteH7Wing (HSE = 16 MHz), VCO = 16/5 * 500 = 1600 MHz, far exceeding the STM32H7 specification. This caused the SDMMC kernel clock (PLL2R = 4) to run at 400 MHz instead of the required 200 MHz. Fix: compute PLL2M from HSE_VALUE (same formula as PLL1M) and reduce PLL2N from 500 to 400, pinning VCO to 800 MHz for any HSE frequency: - HSE=8: M=4, N=400 → VCO=800 MHz - HSE=16: M=8, N=400 → VCO=800 MHz Closes #11594 --- src/main/target/system_stm32h7xx.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/src/main/target/system_stm32h7xx.c b/src/main/target/system_stm32h7xx.c index 6ec0d1c4002..bb4390f487f 100644 --- a/src/main/target/system_stm32h7xx.c +++ b/src/main/target/system_stm32h7xx.c @@ -499,9 +499,9 @@ void SystemClock_Config(void) #ifdef USE_SDCARD_SDIO RCC_PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_SDMMC; - RCC_PeriphClkInit.PLL2.PLL2M = 5; - RCC_PeriphClkInit.PLL2.PLL2N = 500; - RCC_PeriphClkInit.PLL2.PLL2P = 2; // 500Mhz + RCC_PeriphClkInit.PLL2.PLL2M = HSE_VALUE / 1000000 / 2; + RCC_PeriphClkInit.PLL2.PLL2N = 400; + RCC_PeriphClkInit.PLL2.PLL2P = 2; // 200Mhz RCC_PeriphClkInit.PLL2.PLL2Q = 3; // 266Mhz - 133Mhz can be derived from this for for QSPI if flash chip supports the speed. RCC_PeriphClkInit.PLL2.PLL2R = 4; // 200Mhz HAL LIBS REQUIRE 200MHZ SDMMC CLOCK, see HAL_SD_ConfigWideBusOperation, SDMMC_HSpeed_CLK_DIV, SDMMC_NSpeed_CLK_DIV RCC_PeriphClkInit.PLL2.PLL2RGE = RCC_PLL2VCIRANGE_0; From 9570a92d4aba95ef82396adca6222163b57df412 Mon Sep 17 00:00:00 2001 From: daijoubu Date: Thu, 28 May 2026 17:27:28 -0700 Subject: [PATCH 2/2] fix: PLL2P comment shows correct frequency (400Mhz, not 200Mhz) With VCO = 800 MHz, PLL2P = 2 gives 800/2 = 400 MHz. --- src/main/target/system_stm32h7xx.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/main/target/system_stm32h7xx.c b/src/main/target/system_stm32h7xx.c index bb4390f487f..0cd963b46c8 100644 --- a/src/main/target/system_stm32h7xx.c +++ b/src/main/target/system_stm32h7xx.c @@ -501,7 +501,7 @@ void SystemClock_Config(void) RCC_PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_SDMMC; RCC_PeriphClkInit.PLL2.PLL2M = HSE_VALUE / 1000000 / 2; RCC_PeriphClkInit.PLL2.PLL2N = 400; - RCC_PeriphClkInit.PLL2.PLL2P = 2; // 200Mhz + RCC_PeriphClkInit.PLL2.PLL2P = 2; // 400Mhz RCC_PeriphClkInit.PLL2.PLL2Q = 3; // 266Mhz - 133Mhz can be derived from this for for QSPI if flash chip supports the speed. RCC_PeriphClkInit.PLL2.PLL2R = 4; // 200Mhz HAL LIBS REQUIRE 200MHZ SDMMC CLOCK, see HAL_SD_ConfigWideBusOperation, SDMMC_HSpeed_CLK_DIV, SDMMC_NSpeed_CLK_DIV RCC_PeriphClkInit.PLL2.PLL2RGE = RCC_PLL2VCIRANGE_0;