Hold timing fix

[phlfm]

PR Description

The ATF script now implements a two-stage timing closure strategy:

1. Primary fix: phys_opt_design: Post-route physical optimization is attempted first. This pass can resolve many hold violations automatically by adjusting placement and routing within existing constraints.
2. Fallback fix: route_design rerun: If hold violations persist after phys_opt_design, the script reruns route_design as suggested by an AMD employee on the Xilinx forums. This rerun many times is faster than a full route and finally fixes the hold timing issues.

By combining these approaches, the script maximizes the chance of achieving timing closure while preferring the less invasive optimization first.

Related PRs: #1909 and #1966

PR Type

• Bug fix (change that fixes an issue)
• New feature (change that adds new functionality)
• Breaking change (has dependencies in other repos or will cause CI to fail)
• Documentation

PR Checklist

• I have followed the code style guidelines
• I have performed a self-review of changes
• I have compiled all hdl projects and libraries affected by this PR
• I have tested in hardware affected projects, at least on relevant boards
• I have commented my code, at least hard-to-understand parts
• I have signed off all commits from this PR
• I have updated the documentation (wiki pages, ReadMe files, Copyright etc)
• I have not introduced new Warnings/Critical Warnings on compilation
• I have added new hdl testbenches or updated existing ones