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arch/arm64/imx95-a55: add GPIO and eMMC (USDHC) support with partition table parsing #18501

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Merged
xiaoxiang781216 merged 9 commits into from
Mar 24, 2026
Merged

arch/arm64/imx95-a55: add GPIO and eMMC (USDHC) support with partition table parsing #18501

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7dace78
cmake: arm64/common sync modifyreg sources with Make.defs
jasonbu Mar 6, 2026
6a7699a
mmcsd: fix MMC bus width switch using wrong condition and add 8-bit s…
jasonbu Mar 6, 2026
3ffb370
imx9: imx95 fix uSDHC IRQ naming to match NuttX USDHC convention
jasonbu Mar 6, 2026
b5dedaa
imx9: add GPIO support for imx95
jasonbu Mar 6, 2026
0d4447e
imx95-a55-evk: add USDHC eMMC driver support
jasonbu Mar 6, 2026
d69074e
imx9: usdhc fix dmapreflight rejecting small unaligned buffers
jasonbu Mar 6, 2026
fdc9775
imx95-a55-evk: add MBR/GPT partition table parsing on eMMC
jasonbu Mar 6, 2026
9def641
imx95-a55-evk: add emmc defconfig for eMMC 8-bit with partition table
jasonbu Mar 20, 2026
85a62d7
Documentation: imx95-a55-evk: add UMS flashing steps for u-boot
jasonbu Mar 20, 2026
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20 changes: 18 additions & 2 deletions Documentation/platforms/arm64/imx9/boards/imx95-a55-evk/index.rst
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Expand Up @@ -81,9 +81,25 @@ You have four options:
Option 1: load via u-boot from SD-card:
---------------------------------------

1. Build nuttx, and move ``nuttx.bin`` to MMC
1. Build nuttx

2. Load from MMC and start nuttx payload
2. In the u-boot console, expose the eMMC as a USB mass storage device:

.. code:: console

u-boot=> ums 0 mmc 0

The board will appear as a USB drive on the host PC.

3. On the Linux host, copy ``nuttx.bin`` to the boot partition:

.. code:: console

$ cp nuttx.bin /media/`id -un`/boot

4. Go back to the u-boot console and press ``Ctrl+C`` to stop UMS mode.

5. Load from MMC and start nuttx payload:

.. code:: console

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6 changes: 3 additions & 3 deletions arch/arm/include/imx9/imx95_irq.h
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Expand Up @@ -110,8 +110,8 @@
#define IMX9_IRQ_TMPSNS2_THR1 (IMX9_IRQ_EXTINT + 83) /* CORTEXAMIX TempSensor non-secure interrupt from Threshold 1 */
#define IMX9_IRQ_TMPSNS2_THR2 (IMX9_IRQ_EXTINT + 84) /* CORTEXAMIX TempSensor non-secure interrupt from Threshold 2 */
#define IMX9_IRQ_TMPSNS2_DRDY (IMX9_IRQ_EXTINT + 85) /* CORTEXAMIX TempSensor non-secure data ready interrupt */
#define IMX9_IRQ_uSDHC1 (IMX9_IRQ_EXTINT + 86) /* ultra Secure Digital Host Controller interrupt 1 */
#define IMX9_IRQ_uSDHC2 (IMX9_IRQ_EXTINT + 87) /* ultra Secure Digital Host Controller interrupt 2 */
#define IMX9_IRQ_USDHC1 (IMX9_IRQ_EXTINT + 86) /* ultra Secure Digital Host Controller interrupt 1 */
#define IMX9_IRQ_USDHC2 (IMX9_IRQ_EXTINT + 87) /* ultra Secure Digital Host Controller interrupt 2 */
#define IMX9_IRQ_RESERVED104 (IMX9_IRQ_EXTINT + 88) /* MEGAMIX TRDC transfer error interrupt */
#define IMX9_IRQ_RESERVED105 (IMX9_IRQ_EXTINT + 89) /* NIC_WRAPPER TRDC transfer error interrupt */
#define IMX9_IRQ_RESERVED106 (IMX9_IRQ_EXTINT + 90) /* NOCMIX TRDC transfer error interrupt */
Expand Down Expand Up @@ -215,7 +215,7 @@
#define IMX9_IRQ_PDM_EVENT (IMX9_IRQ_EXTINT + 188) /* PDM interrupt */
#define IMX9_IRQ_RESERVED205 (IMX9_IRQ_EXTINT + 189) /* AUDIO XCVR interrupt */
#define IMX9_IRQ_RESERVED206 (IMX9_IRQ_EXTINT + 190) /* AUDIO XCVR interrupt */
#define IMX9_IRQ_uSDHC3 (IMX9_IRQ_EXTINT + 191) /* ultra Secure Digital Host Controller interrupt 3 */
#define IMX9_IRQ_USDHC3 (IMX9_IRQ_EXTINT + 191) /* ultra Secure Digital Host Controller interrupt 3 */
#define IMX9_IRQ_RESERVED208 (IMX9_IRQ_EXTINT + 192) /* OCRAM MECC interrupt */
#define IMX9_IRQ_RESERVED209 (IMX9_IRQ_EXTINT + 193) /* OCRAM MECC interrupt */
#define IMX9_IRQ_RESERVED210 (IMX9_IRQ_EXTINT + 194) /* CM33 MCM interrupt */
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6 changes: 3 additions & 3 deletions arch/arm64/include/imx9/imx95_irq.h
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Expand Up @@ -109,8 +109,8 @@
#define IMX9_IRQ_TMPSNS2_THR1 (IMX9_IRQ_EXT + 83) /* CORTEXAMIX TempSensor non-secure interrupt from Threshold 1 */
#define IMX9_IRQ_TMPSNS2_THR2 (IMX9_IRQ_EXT + 84) /* CORTEXAMIX TempSensor non-secure interrupt from Threshold 2 */
#define IMX9_IRQ_TMPSNS2_DRDY (IMX9_IRQ_EXT + 85) /* CORTEXAMIX TempSensor non-secure data ready interrupt */
#define IMX9_IRQ_uSDHC1 (IMX9_IRQ_EXT + 86) /* ultra Secure Digital Host Controller interrupt 1 */
#define IMX9_IRQ_uSDHC2 (IMX9_IRQ_EXT + 87) /* ultra Secure Digital Host Controller interrupt 2 */
#define IMX9_IRQ_USDHC1 (IMX9_IRQ_EXT + 86) /* ultra Secure Digital Host Controller interrupt 1 */
#define IMX9_IRQ_USDHC2 (IMX9_IRQ_EXT + 87) /* ultra Secure Digital Host Controller interrupt 2 */
#define IMX9_IRQ_RESERVED104 (IMX9_IRQ_EXT + 88) /* MEGAMIX TRDC transfer error interrupt */
#define IMX9_IRQ_RESERVED105 (IMX9_IRQ_EXT + 89) /* NIC_WRAPPER TRDC transfer error interrupt */
#define IMX9_IRQ_RESERVED106 (IMX9_IRQ_EXT + 90) /* NOCMIX TRDC transfer error interrupt */
Expand Down Expand Up @@ -214,7 +214,7 @@
#define IMX9_IRQ_PDM_EVENT (IMX9_IRQ_EXT + 188) /* PDM interrupt */
#define IMX9_IRQ_RESERVED205 (IMX9_IRQ_EXT + 189) /* AUDIO XCVR interrupt */
#define IMX9_IRQ_RESERVED206 (IMX9_IRQ_EXT + 190) /* AUDIO XCVR interrupt */
#define IMX9_IRQ_uSDHC3 (IMX9_IRQ_EXT + 191) /* ultra Secure Digital Host Controller interrupt 3 */
#define IMX9_IRQ_USDHC3 (IMX9_IRQ_EXT + 191) /* ultra Secure Digital Host Controller interrupt 3 */
#define IMX9_IRQ_RESERVED208 (IMX9_IRQ_EXT + 192) /* OCRAM MECC interrupt */
#define IMX9_IRQ_RESERVED209 (IMX9_IRQ_EXT + 193) /* OCRAM MECC interrupt */
#define IMX9_IRQ_RESERVED210 (IMX9_IRQ_EXT + 194) /* CM33 MCM interrupt */
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1 change: 1 addition & 0 deletions arch/arm64/src/common/CMakeLists.txt
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Expand Up @@ -39,6 +39,7 @@ list(APPEND SRCS arm64_perf.c arm64_tcbinfo.c)
list(APPEND SRCS arm64_arch_timer.c arm64_cache.c)
list(APPEND SRCS arm64_doirq.c arm64_fatal.c)
list(APPEND SRCS arm64_syscall.c)
list(APPEND SRCS arm64_modifyreg8.c arm64_modifyreg16.c arm64_modifyreg32.c)

# Use common heap allocation for now (may need to be customized later)
list(APPEND SRCS arm64_allocateheap.c)
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4 changes: 3 additions & 1 deletion arch/arm64/src/imx9/CMakeLists.txt
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Expand Up @@ -24,7 +24,9 @@ set(SRCS imx9_boot.c imx9_clockconfig.c imx9_iomuxc.c imx9_lpuart.c
imx9_lowputc.c)

if(CONFIG_ARCH_CHIP_IMX93)
list(APPEND SRCS imx9_ccm.c imx9_gpio.c)
list(APPEND SRCS imx9_ccm.c imx9_gpio.c imx9_gpiobase.c)
elseif(CONFIG_ARCH_CHIP_IMX95)
list(APPEND SRCS imx9_gpio.c imx9_gpiobase.c)
endif()

if(CONFIG_IMX9_GPIO_IRQ)
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3 changes: 3 additions & 0 deletions arch/arm64/src/imx9/Kconfig
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Expand Up @@ -202,6 +202,9 @@ choice
depends on IMX9_USDHC2
prompt "Bus width for USDHC2"
default IMX9_USDHC2_WIDTH_D1_D4
---help---
USDHC2 supports up to 4-bit data width only according to chip
spec. No 8-bit option is provided.

config IMX9_USDHC2_WIDTH_D1_ONLY
bool "One bit"
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4 changes: 3 additions & 1 deletion arch/arm64/src/imx9/Make.defs
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Expand Up @@ -31,7 +31,9 @@ endif
CHIP_CSRCS = imx9_boot.c

ifeq ($(CONFIG_ARCH_CHIP_IMX93),y)
CHIP_CSRCS += imx9_ccm.c imx9_gpio.c
CHIP_CSRCS += imx9_ccm.c imx9_gpio.c imx9_gpiobase.c
else ifeq ($(CONFIG_ARCH_CHIP_IMX95),y)
CHIP_CSRCS += imx9_gpio.c imx9_gpiobase.c
endif

CHIP_CSRCS += imx9_lpuart.c imx9_lowputc.c imx9_clockconfig.c
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12 changes: 6 additions & 6 deletions arch/arm64/src/imx9/hardware/imx93/imx93_pll.h
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Expand Up @@ -104,12 +104,12 @@

/* DRAMPLL registers */

#define DRAMPLL_CTRL (IMX9_AUDIOPLL_BASE + PLL_CTRL_OFFSET)
#define DRAMPLL_SPREAD_SPECTRUM (IMX9_AUDIOPLL_BASE + PLL_SPREAD_SPECTRUM_OFFSET)
#define DRAMPLL_NUMERATOR (IMX9_AUDIOPLL_BASE + PLL_NUMERATOR_OFFSET)
#define DRAMPLL_DENOMINATOR (IMX9_AUDIOPLL_BASE + PLL_DENOMINATOR_OFFSET)
#define DRAMPLL_DIV (IMX9_AUDIOPLL_BASE + PLL_DIV_OFFSET)
#define DRAMPLL_PLL_STATUS (IMX9_AUDIOPLL_BASE + PLL_PLL_STATUS_OFFSET)
#define DRAMPLL_CTRL (IMX9_DRAMPLL_BASE + PLL_CTRL_OFFSET)
#define DRAMPLL_SPREAD_SPECTRUM (IMX9_DRAMPLL_BASE + PLL_SPREAD_SPECTRUM_OFFSET)
#define DRAMPLL_NUMERATOR (IMX9_DRAMPLL_BASE + PLL_NUMERATOR_OFFSET)
#define DRAMPLL_DENOMINATOR (IMX9_DRAMPLL_BASE + PLL_DENOMINATOR_OFFSET)
#define DRAMPLL_DIV (IMX9_DRAMPLL_BASE + PLL_DIV_OFFSET)
#define DRAMPLL_PLL_STATUS (IMX9_DRAMPLL_BASE + PLL_PLL_STATUS_OFFSET)

/* VIDEOPLL registers */

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