arch/arm/gd21f4: Gd32f470vit6 port

arch/arm/src/gd32f4/CMakeLists.txt

@@ -66,4 +66,8 @@ if(CONFIG_GD32F4_SDIO)
   list(APPEND SRCS gd32f4xx_sdio.c)
 endif()
 
+if(CONFIG_GD32F4_CAN)
+  list(APPEND SRCS gd32f4xx_can.c)
+endif()
+
 target_sources(arch PRIVATE ${SRCS})

arch/arm/src/gd32f4/Kconfig

@@ -192,6 +192,79 @@ config GD32F4_DFU
 		Configure and position code for use with the GD MCU DFU bootloader.  Do
 		not select this option if you will load code using JTAG/SWM.
 
+config GD32F4_HAVE_OTA_PARTITION
+	bool
+	default n
+
+choice
+	prompt "Application Image Format"
+	depends on ARCH_CHIP_GD32F4
+	default GD32F4_APP_FORMAT_LEGACY
+
+config GD32F4_APP_FORMAT_LEGACY
+	bool "Legacy format"
+
+config GD32F4_APP_FORMAT_MCUBOOT
+	bool "MCUboot-bootable format"
+	select GD32F4_HAVE_OTA_PARTITION
+	depends on EXPERIMENTAL
+
+endchoice # Application Image Format
+
+if GD32F4_HAVE_OTA_PARTITION
+
+config GD32F4_MCUBOOT_HEADER_SIZE
+	hex "MCUboot image header size"
+	default 0x200
+	depends on GD32F4_APP_FORMAT_MCUBOOT
+
+menuconfig GD32F4_PROGMEM_OTA_PARTITION
+	bool "MTD driver for OTA partition"
+	default n
+	depends on GD32F4_APP_FORMAT_MCUBOOT
+	select BCH
+	select MTD
+	select MTD_BYTE_WRITE
+	select MTD_PARTITION
+	select MTD_PROGMEM
+	select GD32F4_PROGMEM
+
+if GD32F4_PROGMEM_OTA_PARTITION
+
+config GD32F4_OTA_PRIMARY_SLOT_DEVPATH
+	string "Primary slot device path"
+	default "/dev/ota0"
+
+config GD32F4_OTA_SECONDARY_SLOT_DEVPATH
+	string "Secondary slot device path"
+	default "/dev/ota1"
+
+config GD32F4_OTA_SCRATCH_DEVPATH
+	string "Scratch partition device path"
+	default "/dev/otascratch"
+
+config GD32F4_OTA_PRIMARY_SLOT_OFFSET
+	hex "Primary slot offset"
+	default 0x20000
+
+config GD32F4_OTA_SECONDARY_SLOT_OFFSET
+	hex "Secondary slot offset"
+	default 0x100000
+
+config GD32F4_OTA_SCRATCH_OFFSET
+	hex "Scratch partition offset"
+	default 0x1e0000
+
+config GD32F4_OTA_SLOT_SIZE
+	hex "Application image slot size (in bytes)"
+	default 0xe0000
+
+config GD32F4_OTA_SCRATCH_SIZE
+	hex "Scratch partition size (in bytes)"
+	default 0x20000
+
+endif # GD32F4_PROGMEM_OTA_PARTITION
+endif # GD32F4_HAVE_OTA_PARTITION
 
 menu "GD32 Peripheral Support"
 
@@ -270,12 +343,14 @@ config GD32F4_BKPSRAM
 config GD32F4_CAN0
 	bool "CAN0"
 	select CAN
+	select ARCH_HAVE_CAN_ERRORS
 	select GD32F4_CAN
 	default n
 
 config GD32F4_CAN1
 	bool "CAN1"
 	select CAN
+	select ARCH_HAVE_CAN_ERRORS
 	select GD32F4_CAN
 	default n
 
@@ -1820,7 +1895,7 @@ config USART5_RS485_DIR_POLARITY
 	int "Configure USART5 RS-485 DIR pin polarity"
 	default 1
 	range 0 1
-	depends on USART1_RS485
+	depends on USART5_RS485
 	---help---
 		Polarity of GPIO_USART5_RS485_DIR pin for RS-485 on USART5.
 		The state on DIR pin: 0 - receive , 1 - transmit.
@@ -2582,6 +2657,44 @@ config GD32F4_USB_ITRMP
 menu "CAN driver configuration"
 	depends on GD32F4_CAN
 
+config GD32F4_CAN0_BAUD
+	int "CAN0 BAUD"
+	depends on GD32F4_CAN0
+	default 500000
+	---help---
+		CAN0 BAUD rate.  Required if CONFIG_GD32F4_CAN0 is defined.
+		Default 500000 for Board1 Power CAN MVP.
+
+config GD32F4_CAN1_BAUD
+	int "CAN1 BAUD"
+	depends on GD32F4_CAN1
+	default 500000
+	---help---
+		CAN1 BAUD rate.  Required if CONFIG_GD32F4_CAN1 is defined.
+
+config GD32F4_CAN_TSEG1
+	int "TSEG1 quanta"
+	default 6
+	---help---
+		The number of CAN time quanta in segment 1. Default: 6
+		(bit time = TSEG1 + TSEG2 + 1 = 14 quanta with default TSEG2).
+
+config GD32F4_CAN_TSEG2
+	int "TSEG2 quanta"
+	default 7
+	---help---
+		The number of CAN time quanta in segment 2. Default: 7
+
+config GD32F4_CAN_REGDEBUG
+	bool "CAN Register level debug"
+	depends on DEBUG_CAN_INFO
+	default n
+	---help---
+		Output detailed register-level CAN device debug information.
+		Requires also CONFIG_DEBUG_CAN_INFO.
+
+comment "Loopback mode uses Device Drivers -> CAN Driver Support -> CONFIG_CAN_LOOPBACK"
+
 endmenu # "CAN driver configuration"
 
 

arch/arm/src/gd32f4/Make.defs

@@ -64,3 +64,7 @@ endif
 ifeq ($(CONFIG_GD32F4_SDIO),y)
 CHIP_CSRCS += gd32f4xx_sdio.c
 endif
+
+ifeq ($(CONFIG_GD32F4_CAN),y)
+CHIP_CSRCS += gd32f4xx_can.c
+endif

arch/arm/src/gd32f4/gd32f4xx.h

@@ -50,5 +50,6 @@
 #include "gd32f4xx_i2c.h"
 #include "gd32f4xx_syscfg.h"
 #include "gd32f4xx_sdio.h"
+#include "gd32f4xx_can.h"
 
 #endif /* __ARCH_ARM_SRC_GD32F4_GD32F4XX_H */