Add busperf integration (PoC) - #4633
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Signed-off-by: Robert Winkler <rwinkler@antmicro.com>
Signed-off-by: Robert Winkler <rwinkler@antmicro.com>
Signed-off-by: Robert Winkler <rwinkler@antmicro.com>
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This pull request adds support for busperf analyzer that can be used to measure stalls on various bus interfaces in digital designs. The integration provides a way to automatically generate the configuration file for busperf that can be used in SystemVerilog simulation in a broader system. The provided functionality does not require any instrumentation on the design side.
It adds a set of Bazel rules:
xls_busperf_yamlto generate the bus description from a DSLX proc,busperf_analyzeto run busperf against a VCD and produce a text or HTML report.Signature generation in the main codegen toolchain was extended so a block's signature embeds its instantiated children's signatures recursively. This lets the bus description cover internal channels between a parent proc and its spawned children, not just the design's external interface.
A full worked example is included under
xls/experimental/busperf/examples/, comparing a stalling and a healthypipeline side by side. See xls/experimental/busperf/README.md and examples/README.md for usage and the exact commands to reproduce it.
Here is the final HTML report generated from the example with stalls, that reports observable backpressure
