STM32H7: PLL1 configured with wrong VCIRANGE (VCIRANGE_2 used for 2 MHz VCI input)

[daijoubu]

Summary

In src/main/target/system_stm32h7xx.c, PLL1 is configured with RCC_PLL1VCIRANGE_2 (covers 4–8 MHz VCI input range), but the actual VCI input to PLL1 is 2 MHz on all standard H7 targets.

Details

File: src/main/target/system_stm32h7xx.c
Line: ~305

RCC_OscInitStruct.PLL.PLLRGE = RCC_PLL1VCIRANGE_2;  // selects 4–8 MHz range

PLL1M is computed as HSE_VALUE / 1000000 / 2, giving:

• 8 MHz HSE → M=4 → VCI = 8/4 = 2 MHz
• 16 MHz HSE (KAKUTEH7WING) → M=8 → VCI = 16/8 = 2 MHz

Per the STM32H7 reference manual (RM0433 section 8.7.12), the VCI ranges are:

• VCIRANGE_0: 1–2 MHz
• VCIRANGE_1: 2–4 MHz ← correct for 2 MHz VCI
• VCIRANGE_2: 4–8 MHz ← currently used, but VCI is only 2 MHz
• VCIRANGE_3: 8–16 MHz

The correct setting is RCC_PLL1VCIRANGE_1 (or RCC_PLL1VCIRANGE_0 if 2 MHz is considered the inclusive lower boundary of that range).

Impact

The wrong VCIRANGE affects the PLL charge pump calibration. The PLL may still lock in practice due to silicon tolerance, which is likely why this has gone unnoticed. However it is outside specification and may cause:

• Increased PLL jitter
• Marginal lock behaviour under temperature/voltage stress
• Potential instability on borderline hardware

Affected Targets

All STM32H7 targets (the formula and VCIRANGE setting are shared).

Fix

Change line ~305 from:

RCC_OscInitStruct.PLL.PLLRGE = RCC_PLL1VCIRANGE_2;

to:

RCC_OscInitStruct.PLL.PLLRGE = RCC_PLL1VCIRANGE_1;