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Add support for PCIe switches in indus mezz board #219

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915211c
FROMLIST: arm64: dts: qcom: qcs6490-rb3gen2-industrial-mezzanine: Add…
Feb 3, 2026
adf368c
FROMLIST: arm64: dts: qcom: qcs6490-rb3gen2-industrial-mezzanine: Add…
Feb 3, 2026
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234 changes: 234 additions & 0 deletions arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-industrial-mezzanine.dtso
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Original file line number Diff line number Diff line change
Expand Up @@ -5,9 +5,47 @@

/dts-v1/;
/plugin/;
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/clock/qcom,gcc-sc7280.h>
#include <dt-bindings/pinctrl/qcom,pmic-gpio.h>

&{/} {

vreg_dc_12v: regulator-vreg-dc-12v {
compatible = "regulator-fixed";
regulator-name = "VREG_DC_12V";

regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <24000000>;
regulator-max-microvolt = <24000000>;
};

vreg_1p8: regulator-vreg-1p8 {
compatible = "regulator-fixed";
regulator-name = "VREG_1P8";

regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;

vin-supply = <&vreg_dc_12v>;
};

vreg_0p9: regulator-vreg-0p9 {
compatible = "regulator-fixed";
regulator-name = "VREG_0P9";

regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <900000>;
regulator-max-microvolt = <900000>;

vin-supply = <&vreg_dc_12v>;
};
};

&spi11 {
#address-cells = <1>;
#size-cells = <0>;
Expand All @@ -19,3 +57,199 @@
spi-max-frequency = <20000000>;
};
};

&pcie0 {
bus-range = <0x00 0xff>;
iommu-map = <0x0 &apps_smmu 0x1c00 0x1>,
<0x100 &apps_smmu 0x1c01 0x1>,
<0x208 &apps_smmu 0x1c04 0x1>,
<0x210 &apps_smmu 0x1c05 0x1>,
<0x218 &apps_smmu 0x1c06 0x1>,
<0x300 &apps_smmu 0x1c07 0x1>,
<0x400 &apps_smmu 0x1c08 0x1>,
<0x500 &apps_smmu 0x1c09 0x1>,
<0x501 &apps_smmu 0x1c10 0x1>;

status = "okay";
};

&pcie0_phy {
vdda-phy-supply = <&vreg_l10c_0p88>;
vdda-pll-supply = <&vreg_l6b_1p2>;

status = "okay";
};

&pcie0_port {
pcie0_switch0_usp: pcie@0,0 {
compatible = "pci1179,0623";
reg = <0x10000 0x0 0x0 0x0 0x0>;
#address-cells = <3>;
#size-cells = <2>;

device_type = "pci";
ranges;

vddc-supply = <&vreg_0p9>;
vdd18-supply = <&vreg_1p8>;
vdd09-supply = <&vreg_0p9>;
vddio1-supply = <&vreg_1p8>;
vddio2-supply = <&vreg_1p8>;
vddio18-supply = <&vreg_1p8>;

i2c-parent = <&i2c1 0x77>;

resx-gpios = <&tlmm 78 GPIO_ACTIVE_LOW>;

pinctrl-0 = <&pcie0_tc9563_resx_n>;
pinctrl-names = "default";

pcie0_switch0_dsp1: pcie@1,0 {
reg = <0x20800 0x0 0x0 0x0 0x0>;
#address-cells = <3>;
#size-cells = <2>;

device_type = "pci";
ranges;
};

pcie0_switch0_dsp2: pcie@2,0 {
reg = <0x21000 0x0 0x0 0x0 0x0>;
#address-cells = <3>;
#size-cells = <2>;

device_type = "pci";
ranges;
};

pcie0_switch0_dsp3: pcie@3,0 {
reg = <0x21800 0x0 0x0 0x0 0x0>;
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
ranges;

pcie0_switch0_eth0: pci@0,0 {
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
ranges;
};

pcie0_switch0_eth1: pci@0,1 {
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
ranges;
};
};
};
};

&pcie1 {
iommu-map = <0x0 &apps_smmu 0x1c80 0x1>,
<0x100 &apps_smmu 0x1c81 0x1>,
<0x208 &apps_smmu 0x1c84 0x1>,
<0x210 &apps_smmu 0x1c85 0x1>,
<0x218 &apps_smmu 0x1c86 0x1>,
<0x300 &apps_smmu 0x1c87 0x1>,
<0x408 &apps_smmu 0x1c90 0x1>,
<0x410 &apps_smmu 0x1c91 0x1>,
<0x418 &apps_smmu 0x1c92 0x1>,
<0x500 &apps_smmu 0x1c93 0x1>,
<0x600 &apps_smmu 0x1c94 0x1>,
<0x700 &apps_smmu 0x1c95 0x1>,
<0x701 &apps_smmu 0x1c96 0x1>,
<0x800 &apps_smmu 0x1c97 0x1>,
<0x900 &apps_smmu 0x1c98 0x1>,
<0x901 &apps_smmu 0x1c99 0x1>;
};

&pcie1_switch0_dsp1 {
pcie1_switch1_usp: pcie@0,0 {
compatible = "pci1179,0623";
reg = <0x30000 0x0 0x0 0x0 0x0>;
#address-cells = <3>;
#size-cells = <2>;

device_type = "pci";
ranges;

vddc-supply = <&vdd_ntn_0p9>;
vdd18-supply = <&vdd_ntn_1p8>;
vdd09-supply = <&vdd_ntn_0p9>;
vddio1-supply = <&vdd_ntn_1p8>;
vddio2-supply = <&vdd_ntn_1p8>;
vddio18-supply = <&vdd_ntn_1p8>;

i2c-parent = <&i2c1 0x33>;

resx-gpios = <&tlmm 124 GPIO_ACTIVE_LOW>;

pinctrl-0 = <&pcie1_tc9563_resx_n>;
pinctrl-names = "default";

pcie1_switch1_dsp1: pcie@1,0 {
reg = <0x40800 0x0 0x0 0x0 0x0>;
#address-cells = <3>;
#size-cells = <2>;

device_type = "pci";
ranges;
};

pcie1_switch1_dsp2: pcie@2,0 {
reg = <0x41000 0x0 0x0 0x0 0x0>;
#address-cells = <3>;
#size-cells = <2>;

device_type = "pci";
ranges;
};

pcie1_switch1_dsp3: pcie@3,0 {
reg = <0x41800 0x0 0x0 0x0 0x0>;
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
ranges;

pcie1_switch1_eth0: pci@0,0 {
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
ranges;
};

pcie1_switch1_eth1: pci@0,1 {
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
ranges;
};
};
};
};

&tlmm {
pcie0_tc9563_resx_n: pcie0-tc9563-resx-state {
pins = "gpio78";
function = "gpio";

bias-disable;
input-disable;
output-enable;
power-source = <0>;
};

pcie1_tc9563_resx_n: pcie1-tc9563-resx-state {
pins = "gpio124";
function = "gpio";

bias-disable;
input-disable;
output-enable;
power-source = <0>;
};

};
12 changes: 6 additions & 6 deletions arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts
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Original file line number Diff line number Diff line change
Expand Up @@ -868,7 +868,7 @@
};

&pcie1_port0 {
pcie@0,0 {
pcie1_switch0_usp: pcie@0,0 {
compatible = "pci1179,0623";
reg = <0x10000 0x0 0x0 0x0 0x0>;
#address-cells = <3>;
Expand All @@ -892,7 +892,7 @@
pinctrl-0 = <&tc9563_rsex_n>;
pinctrl-names = "default";

pcie@1,0 {
pcie1_switch0_dsp1: pcie@1,0 {
reg = <0x20800 0x0 0x0 0x0 0x0>;
#address-cells = <3>;
#size-cells = <2>;
Expand All @@ -902,7 +902,7 @@
bus-range = <0x3 0xff>;
};

pcie@2,0 {
pcie1_switch0_dsp2: pcie@2,0 {
reg = <0x21000 0x0 0x0 0x0 0x0>;
#address-cells = <3>;
#size-cells = <2>;
Expand All @@ -912,23 +912,23 @@
bus-range = <0x4 0xff>;
};

pcie@3,0 {
pcie1_switch0_dsp3: pcie@3,0 {
reg = <0x21800 0x0 0x0 0x0 0x0>;
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
ranges;
bus-range = <0x5 0xff>;

pci@0,0 {
pcie1_switch0_eth0: pci@0,0 {
reg = <0x50000 0x0 0x0 0x0 0x0>;
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
ranges;
};

pci@0,1 {
pcie1_switch0_eth1: pci@0,1 {
reg = <0x50100 0x0 0x0 0x0 0x0>;
#address-cells = <3>;
#size-cells = <2>;
Expand Down