Allow vector types for amdgpu

compiler/rustc_monomorphize/src/mono_checks/abi_check.rs

@@ -54,7 +54,7 @@ fn do_check_simd_vector_abi<'tcx>(
                     continue;
                 }
             };
-            if !have_feature(Symbol::intern(feature)) {
+            if !feature.is_empty() && !have_feature(Symbol::intern(feature)) {
                 // Emit error.
                 let (span, _hir_id) = loc();
                 tcx.dcx().emit_err(errors::AbiErrorDisabledVectorType {

compiler/rustc_target/src/target_features.rs

@@ -918,6 +918,7 @@ const AARCH64_FEATURES_FOR_CORRECT_VECTOR_ABI: &'static [(u64, &'static str)] =
 // We might want to add "helium" too.
 const ARM_FEATURES_FOR_CORRECT_VECTOR_ABI: &'static [(u64, &'static str)] = &[(128, "neon")];
 
+const AMDGPU_FEATURES_FOR_CORRECT_VECTOR_ABI: &'static [(u64, &'static str)] = &[(1024, "")];
 const POWERPC_FEATURES_FOR_CORRECT_VECTOR_ABI: &'static [(u64, &'static str)] = &[(128, "altivec")];
 const WASM_FEATURES_FOR_CORRECT_VECTOR_ABI: &'static [(u64, &'static str)] = &[(128, "simd128")];
 const S390X_FEATURES_FOR_CORRECT_VECTOR_ABI: &'static [(u64, &'static str)] = &[(128, "vector")];
@@ -996,12 +997,12 @@ impl Target {
             Arch::Mips | Arch::Mips32r6 | Arch::Mips64 | Arch::Mips64r6 => {
                 MIPS_FEATURES_FOR_CORRECT_VECTOR_ABI
             }
+            Arch::AmdGpu => AMDGPU_FEATURES_FOR_CORRECT_VECTOR_ABI,
             Arch::Nvptx64 | Arch::Bpf | Arch::M68k => &[], // no vector ABI
             Arch::CSky => CSKY_FEATURES_FOR_CORRECT_VECTOR_ABI,
             // FIXME: for some tier3 targets, we are overly cautious and always give warnings
             // when passing args in vector registers.
-            Arch::AmdGpu
-            | Arch::Avr
+            Arch::Avr
             | Arch::Msp430
             | Arch::PowerPC64LE
             | Arch::SpirV

tests/run-make/simd-ffi/rmake.rs

@@ -17,6 +17,9 @@ fn main() {
             "arm-unknown-linux-gnueabi".to_owned(),
         ]);
     }
+    if llvm_components_contain("amdgpu") {
+        targets.push("amdgcn-amd-amdhsa".to_owned());
+    }
     let mut x86_archs = Vec::new();
     if llvm_components_contain("x86") {
         x86_archs.append(&mut vec!["i686", "x86_64"]);
@@ -52,21 +55,25 @@ fn main() {
         // enabled by-default for i686 and ARM; these features will be invalid
         // on some platforms, but LLVM just prints a warning so that's fine for
         // now.
+        let mut cmd = rustc();
+        cmd.target(&target).emit("llvm-ir,asm").input("simd.rs");
         let target_feature = if target.starts_with("i686") || target.starts_with("x86") {
             "+sse2"
         } else if target.starts_with("arm") || target.starts_with("aarch64") {
             "-soft-float,+neon"
         } else if target.starts_with("mips") {
             "+msa,+fp64"
+        } else if target.starts_with("amdgcn") {
+            cmd.arg("-Ctarget-cpu=gfx900");
+            ""
         } else {
             panic!("missing target_feature case for {target}");
         };
-        rustc()
-            .target(&target)
-            .emit("llvm-ir,asm")
-            .input("simd.rs")
-            .arg(format!("-Ctarget-feature={target_feature}"))
-            .arg(&format!("-Cextra-filename=-{target}"))
-            .run();
+
+        if !target_feature.is_empty() {
+            cmd.arg(format!("-Ctarget-feature={target_feature}"));
+        }
+
+        cmd.arg(&format!("-Cextra-filename=-{target}")).run();
     }
 }