ASoC: SOF: Intel: Fix pipeline state transitions for aggregate DAIs#5765
ASoC: SOF: Intel: Fix pipeline state transitions for aggregate DAIs#5765ujfalusi wants to merge 1 commit into
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Pull request overview
This PR fixes IPC4 pipeline state transitions for aggregate back-end links (num_cpus > 1) where multiple CPU DAIs may share the same SOF pipeline, which can currently cause premature RUNNING transitions and redundant PAUSED IPCs.
Changes:
- Add a per-pipeline
trigger_countto gate START/PAUSE_RELEASE so RUNNING is sent only after all DAIs sharing a pipeline have completed link DMA triggering. - Deduplicate STOP/SUSPEND/PAUSE_PUSH PAUSED IPCs for shared pipelines by checking the current pipeline state.
- Compute the “DAIs-per-pipeline” threshold dynamically per BE link to support shared/independent/mixed aggregate topologies.
Reviewed changes
Copilot reviewed 2 out of 2 changed files in this pull request and generated 2 comments.
| File | Description |
|---|---|
| sound/soc/sof/sof-audio.h | Adds trigger_count to struct snd_sof_pipeline to track aggregate trigger completion per pipeline. |
| sound/soc/sof/intel/hda-dai-ops.c | Adds per-pipeline DAI counting and uses trigger_count to gate RUNNING/PAUSED IPC transitions for aggregate DAIs. |
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| if (!w) | ||
| continue; | ||
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| sw = w->dobj.private; |
| int spipe_dais = hda_ipc4_count_spipe_dais(substream, | ||
| swidget->spipe); | ||
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| swidget->spipe->trigger_count++; | ||
| swidget->spipe->started_count++; | ||
| if (swidget->spipe->trigger_count < spipe_dais) | ||
| break; |
kv2019i
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Please check the copilot comment on defensive programming. Otherwise complex, but looks good to me.
| if (!w) | ||
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| sw = w->dobj.private; |
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Changes since v1:
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For aggregate DAIs (num_cpus > 1) the pre_trigger/post_trigger callbacks send pipeline state IPCs per-DAI without considering that multiple DAIs may share the same pipeline. This causes premature state transitions where the pipeline goes RUNNING before all link DMAs have started, or individual DAIs send redundant IPCs for shared pipelines. Fix this by checking the HDA stream running state in post_trigger: - START/PAUSE_RELEASE: defer RUNNING IPC until all DAIs sharing the same pipeline have their link DMA streams running - STOP/SUSPEND/PAUSE_PUSH: use pipeline state dedup so the PAUSED IPC is sent once regardless of how many DAIs share the pipeline The running-state check naturally handles all aggregate topologies: shared pipelines, independent pipelines, and mixed cases without requiring per-pipeline counters. Signed-off-by: Peter Ujfalusi <peter.ujfalusi@linux.intel.com>
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Changes since v2: new approach to drop the changes outside of sof/intel code
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| /* | ||
| * For aggregated DAIs (num_cpus > 1), defer pipeline RUNNING | ||
| * IPC until all CPU DAIs sharing this pipeline have started | ||
| * their link DMAs via hda_trigger(). The running state of each | ||
| * DAI's HDA stream naturally tracks completion. | ||
| */ | ||
| if (num_cpus > 1 && | ||
| !hda_ipc4_all_spipe_dmas_running(substream, swidget->spipe)) | ||
| break; |
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the PR description has been updated...
| /* | ||
| * STOP/SUSPEND trigger is invoked only once when all users of this pipeline have | ||
| * been stopped. So, clear the started_count so that the pipeline can be reset | ||
| * been stopped. So, clear the started_count so that the pipeline can be reset. | ||
| */ | ||
| swidget->spipe->started_count = 0; |
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this change should be removed, it is not related to topic.
For aggregate DAIs (num_cpus > 1) the pre_trigger/post_trigger callbacks
send pipeline state IPCs per-DAI without considering that multiple DAIs
may share the same pipeline. This causes premature state transitions
where the pipeline goes RUNNING before all link DMAs have started, or
individual DAIs send redundant IPCs for shared pipelines.
Fix this by checking the HDA stream running state in post_trigger:
same pipeline have their link DMA streams running
is sent once regardless of how many DAIs share the pipeline
The running-state check naturally handles all aggregate topologies:
shared pipelines, independent pipelines, and mixed cases without
requiring per-pipeline counters.