Adds new STM32 Bare support for Hash, SAES/AES and PKA#13
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dgarske wants to merge 1 commit intowolfSSL:mainfrom
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Adds new STM32 Bare support for Hash, SAES/AES and PKA#13dgarske wants to merge 1 commit intowolfSSL:mainfrom
dgarske wants to merge 1 commit intowolfSSL:mainfrom
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Pull request overview
Adds a new STM32_Bare_Test/ example project to run wolfCrypt tests/benchmarks on multiple STM32 boards without HAL, using direct-register CMSIS startup/linker + per-board bring-up code and a shared user_settings.h configuration.
Changes:
- Introduces a multi-board, multi-config (
c/asm/bare) build system (Makefile + user settings) for bare-metal wolfCrypt validation. - Adds portable board abstraction (
board.h) plustest/benchentry points and minimal newlib syscall stubs for bare-metal. - Adds board-specific startup, linker scripts, CMSIS
System*files (where present), and direct-register clock/UART/SysTick init for several STM32 families.
Reviewed changes
Copilot reviewed 35 out of 35 changed files in this pull request and generated 17 comments.
Show a summary per file
| File | Description |
|---|---|
| STM32_Bare_Test/.gitignore | Ignores build outputs for the new example. |
| STM32_Bare_Test/Makefile | Adds a cross-compile + flash workflow with per-board build settings and selectable configs/targets. |
| STM32_Bare_Test/README.md | Documents supported boards/configs and provides benchmark/test usage notes and results. |
| STM32_Bare_Test/user_settings.h | Centralizes wolfSSL/wolfCrypt feature selection by board and build flavor. |
| STM32_Bare_Test/include/board.h | Defines a minimal portable board API used by test/bench entry points. |
| STM32_Bare_Test/src/main_test.c | Bare-metal wolfCrypt KAT runner (plus optional full wolfcrypt test suite). |
| STM32_Bare_Test/src/main_bench.c | Bare-metal wolfCrypt benchmark runner. |
| STM32_Bare_Test/src/stubs.c | Provides minimal newlib syscall stubs and a basic time() implementation for bare-metal. |
| STM32_Bare_Test/boards/h5/hw_init.c | H5 (H563) direct-register clock/UART/SysTick bring-up and board API implementation. |
| STM32_Bare_Test/boards/h5/startup_stm32h563xx.s | H5 startup/vector table for GCC toolchain. |
| STM32_Bare_Test/boards/h5/stm32h563_flat.ld | H5 linker script defining memory layout and heap/stack boundaries. |
| STM32_Bare_Test/boards/h5/system_stm32h5xx.c | H5 CMSIS SystemInit/SystemCoreClockUpdate implementation. |
| STM32_Bare_Test/boards/h7/hw_init.c | H7 (H753) direct-register PLL/clock/UART/SysTick bring-up and board API implementation. |
| STM32_Bare_Test/boards/h7/startup_stm32h753xx.s | H7 startup/vector table for GCC toolchain. |
| STM32_Bare_Test/boards/h7/stm32h753_flat.ld | H7 linker script defining memory layout and heap/stack boundaries. |
| STM32_Bare_Test/boards/u5/hw_init.c | U5 (U575) direct-register clock/UART/SysTick bring-up and board API implementation. |
| STM32_Bare_Test/boards/u5/startup_stm32u575xx.s | U5 startup/vector table for GCC toolchain. |
| STM32_Bare_Test/boards/u5/stm32u575_flat.ld | U5 linker script defining memory layout and heap/stack boundaries. |
| STM32_Bare_Test/boards/u5/system_stm32u5xx.c | U5 CMSIS SystemInit/SystemCoreClockUpdate implementation. |
| STM32_Bare_Test/boards/u3/hw_init.c | U3 (U385) direct-register clock/UART/SysTick bring-up and board API implementation. |
| STM32_Bare_Test/boards/u3/startup_stm32u385xx.s | U3 startup/vector table for GCC toolchain. |
| STM32_Bare_Test/boards/u3/stm32u385_flat.ld | U3 linker script defining memory layout and heap/stack boundaries. |
| STM32_Bare_Test/boards/u3/system_stm32u3xx.c | U3 CMSIS SystemInit/SystemCoreClockUpdate implementation. |
| STM32_Bare_Test/boards/wb55/hw_init.c | WB55 direct-register PLL/clock/UART/SysTick bring-up and board API implementation. |
| STM32_Bare_Test/boards/wb55/startup_stm32wb55xx.s | WB55 startup/vector table for GCC toolchain. |
| STM32_Bare_Test/boards/wb55/stm32wb55_flat.ld | WB55 linker script defining memory layout and heap/stack boundaries. |
| STM32_Bare_Test/boards/wb55/system_stm32wbxx.c | WB55 CMSIS SystemInit/SystemCoreClockUpdate implementation. |
| STM32_Bare_Test/boards/g491/hw_init.c | G491 direct-register PLL/clock/LPUART/SysTick bring-up and board API implementation. |
| STM32_Bare_Test/boards/g491/startup_stm32g491xx.s | G491 startup/vector table for GCC toolchain. |
| STM32_Bare_Test/boards/g491/stm32g491_flat.ld | G491 linker script defining memory layout and heap/stack boundaries. |
| STM32_Bare_Test/boards/g491/system_stm32g4xx.c | G4 CMSIS SystemInit/SystemCoreClockUpdate implementation used by G491. |
| STM32_Bare_Test/boards/f439/hw_init.c | F439 direct-register PLL/clock/UART/SysTick bring-up and board API implementation. |
| STM32_Bare_Test/boards/f439/startup_stm32f439xx.s | F439 startup/vector table for GCC toolchain. |
| STM32_Bare_Test/boards/f439/stm32f439_flat.ld | F439 linker script defining memory layout and heap/stack boundaries. |
| STM32_Bare_Test/boards/f439/system_stm32f4xx.c | F4 CMSIS SystemInit/SystemCoreClockUpdate implementation used by F439. |
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| * Copyright (C) 2026 wolfSSL Inc. | ||
| * | ||
| * Direct-register board init for NUCLEO-U575ZI-Q: | ||
| * - MSI 4 MHz default at reset; keep it as SYSCLK (skip PLL bring-up) |
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| /* USART1: 8N1, oversampling 16. PCLK2 = 4 MHz; BRR = PCLK / baud. */ | ||
| USART1->CR1 = 0; | ||
| USART1->BRR = 16000000u / 115200u; | ||
| USART1->CR1 = USART_CR1_TE | USART_CR1_RE | USART_CR1_UE; |
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| * - HSI 64 MHz at reset; keep it as SYSCLK (no PLL bring-up yet -- the | ||
| * part can run to 480 MHz with PLL but 64 MHz is plenty for first light) |
| MEMORY | ||
| { | ||
| RAM_D1 (xrw) : ORIGIN = 0x24000000, LENGTH = 512K | ||
| DTCMRAM (xrw) : ORIGIN = 0x24000000, LENGTH = 512K |
| (PWR_CR5.R1MODE = 0) is required for HCLK > 150 MHz on G4. FLASH 4 WS | ||
| + prefetch + I/D-cache. **G491RE has no AES peripheral and no HASH; | ||
| the AES block is only on the G4A1xx variant in this G4 sub-family.** | ||
| RNG (HSI48 kernel clock) and PKA hardware are present. |
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| static char *heap_end; | ||
|
|
||
| void *_sbrk(ptrdiff_t incr) | ||
| { |
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| boards/wb55/hw_init.c | ||
| OPENOCD_TARGET := stm32wbx.cfg | ||
| STLINK_SERIAL := 0670FF393738425043094240 | ||
| endif |
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| OPENOCD_TARGET := stm32g4x.cfg | ||
| STLINK_SERIAL := 004D00263133511636303739 | ||
| endif |
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| /* WB55 startup_stm32wb55xx_cm4.s references MB_MEM2 (BLE shared memory). | ||
| * We don't run a BLE stack on M0+ here, but the startup code still copies | ||
| * [_sMB_MEM2 .. _eMB_MEM2] from _siMB_MEM2. Provide an empty region. */ | ||
| ._mb_mem2 (NOLOAD) : | ||
| { | ||
| . = ALIGN(4); | ||
| _sMB_MEM2 = .; | ||
| _eMB_MEM2 = .; | ||
| } >RAM | ||
| _siMB_MEM2 = _sMB_MEM2; | ||
|
|
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| * NOTE: This file currently runs HAND-WRITTEN inline tests for SHA-256 and | ||
| * the hardware RNG path, both of which exercise the WOLFSSL_STM32_BARE | ||
| * datapath end-to-end on real silicon. The full wolfcrypt/test/test.c suite | ||
| * is NOT yet integrated -- it triggers a newlib stdio fault that's still | ||
| * under investigation (the same banner-then-hang seen during early bring-up). |
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