New Verilog samples / update to heuristics to distinguish from Coq #7493
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…d IP - Allow no space between module name and parameter/port list using \s* - Add `pragma` to preprocessor directive match - Allow no space between `always`/`initial` and @ This improves detection of real-world Verilog files such as: - Vivado-generated module stubs like `module name(...)` - Encrypted vendor IP with `pragma protect` - Compact constructs like `always@(posedge clk)` Previously, these were sometimes misclassified as Rocq Prover or Coq.
- Added `module_stub.v`: Vivado-style stub using `module name(...)` syntax with no space - Added `encrypted_module.v`: representative of encrypted IP using `pragma protect` - Modified `button_debounce.v` to include a valid `always@(...)` syntax case These examples demonstrate the heuristic's improved ability to detect real-world Verilog files, including those previously misclassified as Rocq Prover or Coq due to compact or directive-heavy syntax.
lildude
reviewed
Aug 26, 2025
samples/Verilog/button_debounce.v
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| state <= (!reset_n) ? WAIT : next_state; | ||
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| always @ (posedge clk or negedge reset_n) begin | ||
| always@(posedge clk or negedge reset_n) begin |
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We generally don't change samples. It's better to add a new sample.
lildude
reviewed
Dec 12, 2025
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Description
This pull request fixes misclassification of certain
.vVerilog files that were previously identified as Rocq Prover or Coq due to syntax edge cases. These cases include:modulekeyword is followed directly by the port list with no space (e.g.,module foo(...))`pragma protectdirectives (common in encrypted IP cores)always@orinitial@without space before the sensitivity listThe updated
heuristics.ymlpattern broadens the existing Verilog match to allow for:#and(in module declarations`pragmaas a valid Verilog preprocessor directive@inalwaysandinitialblocksTwo new
.vsamples are added to demonstrate these cases, and an existing sample (button_debounce.v) is updated to include a real-world use ofalways@.Checklist:
module_stub.v: Vivado-generated module stubencrypted_module.v: encrypted IP filebutton_debounce.v: Changealways @ (toalways@(to provide an example of the possibility of no whitespace between these operators.Supporting Evidence
always @andalways@are widely used:always @: ~618,000 resultsalways@: ~60,900 resultsalways@:1bitSDR/NCO.v#L36