New Verilog samples / update to heuristics to distinguish from Coq

lib/linguist/heuristics.yml

@@ -970,7 +970,7 @@ disambiguations:
   - language: Rocq Prover
     pattern: '(?:^|\s)(?:Proof|Qed)\.(?:$|\s)|(?:^|\s)Require[ \t]+(Import|Export)\s'
   - language: Verilog
-    pattern: '^[ \t]*module\s+[^\s()]+\s+\#?\(|^[ \t]*`(?:define|ifdef|ifndef|include|timescale)|^[ \t]*always[ \t]+@|^[ \t]*initial[ \t]+(begin|@)'
+    pattern: '^[ \t]*module\s+[^\s()]+\s*\#?\(|^[ \t]*`(?:define|ifdef|ifndef|include|timescale|pragma)|^[ \t]*always[ \t]*@|^[ \t]*initial[ \t]*(begin|@)'
   - language: V
     pattern: '\$(?:if|else)[ \t]|^[ \t]*fn\s+[^\s()]+\(.*?\).*?\{|^[ \t]*for\s*\{'
 - extensions: ['.vba']

samples/Verilog/encrypted_module.v

@@ -0,0 +1,76 @@
+`pragma protect begin_protected
+`pragma protect version = 1
+`pragma protect encrypt_agent = "XILINX"
+`pragma protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
+`pragma protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
+`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
+`pragma protect key_block
+BtrP/FiKT4cAIn9g/cLi+3bcreZzl8S+GQkeXK138B55MMOjow31+bevhaCy8/OUqRJOXmoFAjjC
+ag+Ia49Vcw==
+
+`pragma protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
+`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
+`pragma protect key_block
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+/mwEj0iblJzgM70crbOp8h1FSZSxWpPeku4OmV17wg2T0IAyS2x3Z8Ln/K8kgDgVlS3dVrh/BulN
+ouU2cu08vQ9CSau3QMA=
+
+`pragma protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
+`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
+`pragma protect key_block
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+XkwA6ltQ4SExC00ka+U=
+
+`pragma protect key_keyowner = "Aldec", key_keyname= "ALDEC15_001", key_method = "rsa"
+`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
+`pragma protect key_block
+FavYF9n1D1ZEqP7w0DJ0F/3BVdRQVBwGrU0Xh14WIw7RznS84eZnydcL51gttmvTUUe2Q/M19qqy
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+UofRED7kkCoKn9YqIq5qt98SWLn/Qpu9O+v/yg==
+
+`pragma protect key_keyowner = "ATRENTA", key_keyname= "ATR-SG-2015-RSA-3", key_method = "rsa"
+`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
+`pragma protect key_block
+KZvW9p2sDxpEFCd9AsiM2YCXm3l9xYlzGVFuonIsAZ/9egCRTWesBtFaLSAhxOwQs0t8G95wYLpy
+29LYXUNxlixAvci0eyV3jiXBbARzQ+mepbTWrQHboCX39Wtgh0x0FyA3tiMfzYIm2mJWjDGbAvbd
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+fnoNuOaGNtV1E8LLSWfMf6uTfIk9zKVeA0i4xQ==
+
+`pragma protect key_keyowner = "Xilinx", key_keyname= "xilinx_2016_05", key_method = "rsa"
+`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
+`pragma protect key_block
+CCaF/36/hLxEK+Qhf7KrAS2FUQgTamDg47PImlUX/X2ecapU9Vqc5AErcJxNzyMCMype3X9UtDrN
+bHQEiStJOIAcxZup6yLKPzpnmJAbbJCibol1+UOvrjJBhJaEy01vjwltiFYYbG3uHKZ+yTbS6f6d
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+vN1mUxtuKy82Aqy3tJqaT7VJ1a0yVxXlLyHq8A==
+
+`pragma protect data_method = "AES128-CBC"
+`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 438576)
+`pragma protect data_block
+U37lCH7MEZplkeIoaPPzYnHBMKwQu/RlhYwrWCai0IIS3Wwea9YtMU4FEAiyAeaH2lsIWSdCjGhm
+dstelEP2SUx0pzDpFU5ZsDxt4PS0AXPsq+An1VW4Jzeh2uhO2F67Oh4qAYJboJKURGZlnTI5RK1q
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+fEFbs9S9D9QJSitqjSnz+2Im
+`pragma protect end_protected

samples/Verilog/module_stub.v

@@ -0,0 +1,26 @@
+// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
+// --------------------------------------------------------------------------------
+// Tool Version: Vivado v.2016.2 (win64) Build 1577090 Thu Jun  2 16:32:40 MDT 2016
+// Date        : Fri May 02 13:58:04 2025
+// Command     : write_verilog -force -mode synth_stub
+// Purpose     : Stub declaration of top-level module interface
+// Device      : xc7k456-2
+// --------------------------------------------------------------------------------
+
+// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
+// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
+// Please paste the declaration into a Verilog source file or add the file as an additional source.
+(* x_core_info = "fifo_generator_v13_1_1,Vivado 2016.2" *)
+module fei4_spy_fifo(rst, wr_clk, rd_clk, din, wr_en, rd_en, dout, full, empty, valid)
+/* synthesis syn_black_box black_box_pad_pin="rst,wr_clk,rd_clk,din[35:0],wr_en,rd_en,dout[35:0],full,empty,valid" */;
+  input rst;
+  input wr_clk;
+  input rd_clk;
+  input [35:0]din;
+  input wr_en;
+  input rd_en;
+  output [35:0]dout;
+  output full;
+  output empty;
+  output valid;
+endmodule