Prepare qcom-next based on tag 'Linux 6.19-rc8' of https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git #218
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Purwa will crash if HLOS attempts to access or configure the TPM pins, as these operations require higher privilege levels. Therefore, the TPM pins should be reserved in the DTS until NHLOS provides proper support. Signed-off-by: Yijie Yang <[email protected]>
…rence boards Document the Kaanapali SoC binding and the boards which use it. Acked-by: Krzysztof Kozlowski <[email protected]> Signed-off-by: Jingyi Wang <[email protected]> Signed-off-by: Yijie Yang <[email protected]> Link: https://lore.kernel.org/all/[email protected]/
Kaanapali is Snapdragon SoC from Qualcomm. Features added in this patch: - CPUs with PSCI idle states and cpufreq - Interrupt-controller with PDC wakeup support - Timers, TCSR Clock Controllers - Reserved Shared memory - GCC and RPMHCC - TLMM - Interconnect with CPU BWMONs - QuP with UART - SMMU - RPMhPD - UFS with Inline Crypto Engine - LLCC - Watchdog - SD Card - PCIe Written with help from Raviteja Laggyshetty (added interconnect nodes), Taniya Das (added Clock Controllers and cpufreq), Jishnu Prakash (added RPMhPD), Nitin Rawat (added UFS), Gaurav Kashyap (added ICE), Manish Pandey (added SD Card) and Qiang Yu (added PCIe). Co-developed-by: Tengfei Fan <[email protected]> Signed-off-by: Tengfei Fan <[email protected]> Signed-off-by: Jingyi Wang <[email protected]> Reviewed-by: Dmitry Baryshkov <[email protected]> Signed-off-by: Yijie Yang <[email protected]> Link: https://lore.kernel.org/all/[email protected]/
Add initial support for Qualcomm Kaanapali MTP board which enables PCIe, SD Card, UFS and booting to shell with UART console. Written with help from Jishnu Prakash (added RPMhPD nodes), Nitin Rawat (added UFS), Manish Pandey (added SD Card) and Qiang Yu (added PCIe). Reviewed-by: Dmitry Baryshkov <[email protected]> Signed-off-by: Jingyi Wang <[email protected]> Reviewed-by: Abel Vesa <[email protected]> Signed-off-by: Yijie Yang <[email protected]> Link: https://lore.kernel.org/all/[email protected]/
Add initial support for Qualcomm Kaanapali QRD board which enables SD Card, UFS and booting to shell with UART console. Written with help from Jishnu Prakash (added RPMhPD nodes), Nitin Rawat (added ufs) and Manish Pandey (added SD Card). Reviewed-by: Dmitry Baryshkov <[email protected]> Signed-off-by: Jingyi Wang <[email protected]> Reviewed-by: Abel Vesa <[email protected]> Signed-off-by: Yijie Yang <[email protected]> Link: https://lore.kernel.org/all/[email protected]/
Hamoa/Purwa currently requires the backlight node from the eDP device, but this macro was overridden by CONFIG_DRM_NOUVEAU. Remove it from prune.config to properly enable the BACKLIGHT_* related config. Signed-off-by: Yongxing Mou <[email protected]>
Remove the old upstream changes; the upstream has already merged the newer version of the changes. Signed-off-by: Shuai Zhang <[email protected]> Link: https://lore.kernel.org/all/[email protected]/
…ller WCN7850 will first attempt to use ELF_TYPE_PATCH, and if that fails, it will fall back to TLV_TYPE_PATCH. To code uniformity, move WCN7850 workaround to the caller. Signed-off-by: Shuai Zhang <[email protected]> Link: https://lore.kernel.org/all/[email protected]/
Add DT node for the kaanapali iris video node. Written with help from Taniya Das(added videocc node). Link: https://lore.kernel.org/all/[email protected]/ Signed-off-by: Vikash Garodia <[email protected]> Signed-off-by: Jingyi Wang <[email protected]>
When PCIe L1ss is enabled, WLAN functionality is completly broken. There are some connectivity issues in this platform mostly with CLKREQ# pin. Disable L1ss as workaround untill actual issue get resolved. Signed-off-by: Krishna Chaitanya Chundru <[email protected]>
…en4 2-lanes PHY The fourth and sixth PCIe instances on Glymur are both Gen4 2-lane PHY. So document the compatible. Link: https://lore.kernel.org/r/20251224-phy-qcom-pcie-add-glymur-v3-1-57396145bc22@oss.qualcomm.com Signed-off-by: Abel Vesa <[email protected]> Reviewed-by: Krzysztof Kozlowski <[email protected]>
Glymur platform has two Gen4 2-lanes controllers, the fourth and sixth instances. Add support for their PHYs. Link: https://lore.kernel.org/r/20251224-phy-qcom-pcie-add-glymur-v3-2-57396145bc22@oss.qualcomm.com Signed-off-by: Abel Vesa <[email protected]> Reviewed-by: Dmitry Baryshkov <[email protected]>
On the Qualcomm Glymur platform the PCIe host is compatible with the DWC controller present on the X1E80100 platform. So document the PCIe controllers found on Glymur and use the X1E80100 compatible string as a fallback in the schema. Link: https://lore.kernel.org/all/[email protected]/ Signed-off-by: Prudhvi Yarlagadda <[email protected]> Signed-off-by: Wenbin Yao <[email protected]> Acked-by: Rob Herring (Arm) <[email protected]> Signed-off-by: Qiang Yu <[email protected]>
… compatible Document compatible for the QMP PCIe PHY on Kaanapali platform. Link: https://lore.kernel.org/all/[email protected]/ Signed-off-by: Jingyi Wang <[email protected]> Reviewed-by: Krzysztof Kozlowski <[email protected]> Reviewed-by: Neil Armstrong <[email protected]> Signed-off-by: Qiang Yu <[email protected]>
…egister offsets Kaanapali SoC uses QMP PHY with version v8 for PCIe Gen3 x2, but requires a completely unique qserdes-txrx register offsets compared to existing v8 offsets. Hence, add a dedicated header file containing the FULL SET of qserdes-txrx register definitions required for Kaanapali's PCIe PHY operation. Link:https://lore.kernel.org/all/[email protected]/ Signed-off-by: Jingyi Wang <[email protected]> Reviewed-by: Dmitry Baryshkov <[email protected]> Reviewed-by: Neil Armstrong <[email protected]> Signed-off-by: Qiang Yu <[email protected]>
Kaanapali SoC uses QMP phy with version v8 for PCIe Gen3 x2. Add the new PCS PCIE specific offsets in a dedicated header file. Link: https://lore.kernel.org/all/[email protected]/ Signed-off-by: Jingyi Wang <[email protected]> Reviewed-by: Dmitry Baryshkov <[email protected]> Reviewed-by: Neil Armstrong <[email protected]> Signed-off-by: Qiang Yu <[email protected]>
Some qserdes-com register offsets for the v8 PHY were previously omitted, as they were not needed by earlier v8 PHY initialization sequences. Add these missing v8 register offsets now required to support PCIe QMP PHY on Kaanapali platform. Link: https://lore.kernel.org/all/[email protected]/ Signed-off-by: Jingyi Wang <[email protected]> Reviewed-by: Dmitry Baryshkov <[email protected]> Reviewed-by: Neil Armstrong <[email protected]> Signed-off-by: Qiang Yu <[email protected]>
Add QMP PCIe PHY support for the Kaanapali platform. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Jingyi Wang <[email protected]> Reviewed-by: Abel Vesa <[email protected]> Reviewed-by: Neil Armstrong <[email protected]> Signed-off-by: Qiang Yu <[email protected]>
…775p
The ACTLR configuration for the sa8775p MDSS client was inadvertently
dropped while reworking the commit f91879fdf70b ("iommu/arm-smmu-qcom:
Add actlr settings for mdss on Qualcomm platforms"). Without this
entry, the sa8775p MDSS block does not receive the intended default
ACTLR configuration.
Restore the missing compatible entry so that the platform receives the
expected behavior.
Link: https://lore.kernel.org/all/[email protected]/
Signed-off-by: Bibek Kumar Patro <[email protected]>
…bypass pwrseq flow There is a conflict between the current DTS configuration and the driver behavior for the WCN6855 Bluetooth path. With the PMU node in place, the driver takes the pwrseq code path unintentionally, which leads to Bluetooth failing to power up during an on -> off -> on transition. To unblock function, temporarily remove the WCN6855 PMU node so that the driver follows the non-pwrseq path and avoids the unexpected sequence. This is a TEMPORARY WORKAROUND. Once a proper M.2 binding/solution is upstreamed, will re-submit both DTS and driver changes aligned with the M.2 model. Signed-off-by: Wei Deng <[email protected]>
…bypass pwrseq flow There is a conflict between the current DTS configuration and the driver behavior for the WCN6855 Bluetooth path. With the PMU node in place, the driver takes the pwrseq code path unintentionally, which leads to Bluetooth failing to power up during an on -> off -> on transition. To unblock function, temporarily remove the WCN6855 PMU node so that the driver follows the non-pwrseq path and avoids the unexpected sequence. This is a TEMPORARY WORKAROUND. Once a proper M.2 binding/solution is upstreamed, will re-submit both DTS and driver changes aligned with the M.2 model. Signed-off-by: Wei Deng <[email protected]>
Document compatible for Qualcomm Kaanapali SoC ADSP PAS which looks fully
compatible with SM8750, which can fallback to SM8550 except for one more
interrupt ("shutdown-ack").
Reviewed-by: Krzysztof Kozlowski <[email protected]>
Signed-off-by: Jingyi Wang <[email protected]>
Link: https://lore.kernel.org/all/[email protected]/
Signed-off-by: Yijie Yang <[email protected]>
Add remote processor PAS loader for Kaanapali CDSP processor, compatible with earlier SM8550 with minor difference: one more sixth "shutdown-ack" interrupt. It is not compatible with SM8650 because one memory region "global_sync_mem" is not managed by kernel on Kaanapali so it is removed in the remoteproc cdsp node. Reviewed-by: Krzysztof Kozlowski <[email protected]> Signed-off-by: Jingyi Wang <[email protected]> Link: https://lore.kernel.org/all/[email protected]/ Signed-off-by: Yijie Yang <[email protected]>
Add qcom,soundwire-v2.2.0 to the list of supported Qualcomm SoundWire controller versions. This version falls back to qcom,soundwire-v2.0.0 if not explicitly handled by the driver. Signed-off-by: Jingyi Wang <[email protected]> Reviewed-by: Krzysztof Kozlowski <[email protected]> Signed-off-by: Prasad Kumpatla <[email protected]> Reviewed-by: Srinivas Kandagatla <[email protected]> Link: https://lore.kernel.org/all/[email protected]/ Signed-off-by: Yijie Yang <[email protected]>
Add CoreSight nodes to enable trace paths such as TPDM->ETF and STM->ETF. These devices are part of the AOSS, CDSP, QDSS, modem and some small subsystems, such as DCC, GCC, ipcc and so on. Reviewed-by: Konrad Dybcio <[email protected]> Signed-off-by: Jie Gan <[email protected]> Signed-off-by: Jingyi Wang <[email protected]> Link: https://lore.kernel.org/all/[email protected]/ Signed-off-by: Yijie Yang <[email protected]>
…rial engines Add device tree support for QUPv3 serial engine protocols on Kaanapali. Kaanapali has 24 QUP serial engines across 4 QUP wrappers, each with support of GPI DMA engines, and it also includes 5 I2C hubs. Signed-off-by: Jyothi Kumar Seerapu <[email protected]> Signed-off-by: Jingyi Wang <[email protected]> Reviewed-by: Dmitry Baryshkov <[email protected]> Link: https://lore.kernel.org/all/[email protected]/ Signed-off-by: Yijie Yang <[email protected]>
The Kaanapali includes seven TSENS instances, with a total of 55 thermal sensors distributed across various locations on the SoC. The TSENS max/reset threshold is configured to 130°C in the hardware. Enable all TSENS instances, and define the thermal zones with a critical trip at 125°C Signed-off-by: Manaf Meethalavalappu Pallikunhi <[email protected]> Signed-off-by: Jingyi Wang <[email protected]> Link: https://lore.kernel.org/all/[email protected]/ Signed-off-by: Yijie Yang <[email protected]>
…i SoC Add remoteproc PAS loader for ADSP and CDSP with its SMP2P and fastrpc nodes. Co-developed-by: Kumari Pallavi <[email protected]> Signed-off-by: Kumari Pallavi <[email protected]> Signed-off-by: Jingyi Wang <[email protected]> Reviewed-by: Dmitry Baryshkov <[email protected]> Link: https://lore.kernel.org/all/[email protected]/ Signed-off-by: Yijie Yang <[email protected]>
Introduce audio support for Kaanapali SoC by adding LPASS macro codecs, TLMM pin controller and SoundWire controller with similar hardware implementation to SM8750 platform. Also add GPR (Generic Pack Router) node along with support for APM (Audio Process Manager) and PRM (Proxy Resource Manager) audio services. Reviewed-by: Konrad Dybcio <[email protected]> Signed-off-by: Prasad Kumpatla <[email protected]> Signed-off-by: Jingyi Wang <[email protected]> Link: https://lore.kernel.org/all/[email protected]/ Signed-off-by: Yijie Yang <[email protected]>
Enable ADSP and CDSP on Kaanapali MTP board. Signed-off-by: Jingyi Wang <[email protected]> Reviewed-by: Dmitry Baryshkov <[email protected]> Link: https://lore.kernel.org/all/[email protected]/ Signed-off-by: Yijie Yang <[email protected]>
# Conflicts: # Documentation/devicetree/bindings/remoteproc/qcom,sm8550-pas.yaml
# Conflicts: # arch/arm64/boot/dts/qcom/Makefile # arch/arm64/boot/dts/qcom/talos.dtsi
# Conflicts: # include/linux/firmware/qcom/qcom_scm.h
Adding merge log file and topic_SHA1 file Signed-off-by: Salendarsingh Gaud <[email protected]>
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Tests-kaanapali-qrd
Tests-lemans-evk
Tests-qcs615-ride
Tests-qcs6490-rb3gen2
Tests-qcs8300-ride
Tests-qcs9100-ride-r3
Tests-sm8750-mtp
Tests-x1e80100-crd
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Tests-kaanapali-qrd
Tests-lemans-evk
Tests-qcs615-ride
Tests-qcs6490-rb3gen2
Tests-qcs8300-ride
Tests-qcs9100-ride-r3
Tests-sm8750-mtp
Tests-x1e80100-crd
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Name SHA Commits
tech/bsp/clk 4a0d4ec 30
tech/bsp/interconnect e9171e9 3
tech/security/firmware-smc a50984a 2
tech/bsp/soc-infra c6c4df7 11
tech/bsp/remoteproc 68d1bd1 19
tech/bus/peripherals 486bcf7 1
tech/bus/pci/all d9f9599 8
tech/bus/usb/dwc 49ac8e0 2
tech/bus/usb/phy 9e7d778 13
tech/debug/hwtracing 88c50d8 27
tech/pmic/misc eaefc12 20
tech/pmic/regulator 81fc8fb 6
tech/mem/iommu 4cff31b 3
tech/mm/audio/all e2e8785 6
tech/mm/camss 84e6e6d 14
tech/mm/drm a5eb28d 32
tech/mm/fastrpc a471773 4
tech/mm/video 4871417 16
tech/mm/gpu 4bb11fd 7
tech/mproc/rpmsg c3875d9 1
tech/net/ath 717323a 22
tech/net/eth c280d7e 1
tech/net/bluetooth b85467e 7
tech/pm/power 7b7e779 7
tech/pm/thermal 363f414 3
tech/security/crypto fa6b06a 11
tech/security/ice 5c53b58 12
tech/storage/all dc1975c 8
tech/all/dt/qcs6490 87b5b8c 7
tech/all/dt/qcs9100 f7d2f96 20
tech/all/dt/qcs8300 c18f558 30
tech/all/dt/qcs615 8e5f8d4 22
tech/all/dt/hamoa e571479 16
tech/all/dt/glymur 390ca2a 27
tech/all/dt/kaanapali c3ff3fc 17
tech/all/dt/pakala b4ebc9f 9
tech/all/config 1d8a949 41
tech/overlay/dt ba99ff1 21
tech/all/workaround 65d2481 4
tech/mproc/all d19a4c1 5
tech/noup/debug/all 8832d0f 6