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Commit f530d37 ("mb/lenovo/x220: Add PCIe ports in CFR") introduced several enum options for "Enabled"/"Disabled" settings. These work like bool options, except that they add extra bloat to the resulting CFR data structures. Replace the enum options with bool options. Also rename the macro as it no longer generates an enum option. While we're at it, properly format "Wi-Fi" and drop a blank line at the start of a file. Also, since checkpatch complains about the macro including a trailing semicolon, drop it from the macro definition and add it at the end of every use of the macro. Change-Id: I7889e22d12e01171ed77ae98d29bbd067e45d82b Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/91340 Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Boolean options are intended to represent generic "Enable"/"Disable" options, but without enum options' extra bloat in the CFR structures. The "volume" option has been left as-is because the code reading its value does not seem to handle it like a boolean. Change-Id: If183957cff6097187904e0d76c7d3ad997fe365c Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/91341 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Boolean options are intended to represent generic "Enable"/"Disable" options, but without enum options' extra bloat in the CFR structures. Change-Id: I3c73f289271eb4bba899bbfe9d3036171cb31d7b Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/91342 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Boolean options are intended to represent generic "Enable"/"Disable" options, but without enum options' extra bloat in the CFR structures. In this case, the callback function already treated the option as if it were a boolean option, which likely only worked by chance. Change-Id: I7e53c791d48bd5ce5271505c59856bf7ff18e6d0 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/91343 Reviewed-by: Caveh Jalali <caveh@chromium.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Boolean options are intended to represent generic "Enable"/"Disable" options, but without enum options' extra bloat in the CFR structures. In this case, the callback function already treated the option as if it were a boolean option, which likely only worked by chance. Change-Id: I747ecd0b5a33d2773eda409e6578362d694154ee Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/91344 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Boolean options are intended to represent generic "Enable"/"Disable" options, but without enum options' extra bloat in the CFR structures. Change-Id: I8f3a69dfb9fb915c44c9a5486512aa82c2615fab Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/91345 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Boolean options are intended to represent generic "Enable"/"Disable" options, but without enum options' extra bloat in the CFR structures. Change-Id: Ib480c7dcd99eb5bf16b124584b4e7dbad90d0c84 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/91346 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Boolean options are intended to represent generic "Enable"/"Disable" options, but without enum options' extra bloat in the CFR structures. Change-Id: I77bfefd0bf173da34675ad64253daae472834bb8 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/91347 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Boolean options are intended to represent generic "Enable"/"Disable" options, but without enum options' extra bloat in the CFR structures. Change-Id: I491f92b334d0e9f98737b94a7232e9361e86743d Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/91348 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Boolean options are intended to represent generic "Enable"/"Disable" options, but without enum options' extra bloat in the CFR structures. Change-Id: I009413db0873c42a98cfc8bddb8613c66d496947 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/91349 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Boolean options are intended to represent generic "Enable"/"Disable" options, but without enum options' extra bloat in the CFR structures. Change-Id: I4be1ac4644c461fd64766e27383e479ff518a889 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/91350 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Boolean options are intended to represent generic "Enable"/"Disable" options, but without enum options' extra bloat in the CFR structures. Change-Id: I4e4f5c071f4299876e4ecd9defe7782c85eac3d8 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/91351 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Boolean options are intended to represent generic "Enable"/"Disable" options, but without enum options' extra bloat in the CFR structures. Change-Id: If9030e770a59d9de87f7b0f2112887db6126aacf Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/91352 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Boolean options are intended to represent generic "Enable"/"Disable" options, but without enum options' extra bloat in the CFR structures. Change-Id: I7f3bb4f13a143e37869c22d66a514581a88deeb2 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/91353 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Boolean options are intended to represent generic "Enable"/"Disable" options, but without enum options' extra bloat in the CFR structures. Change-Id: I3ac872881627179cb4ef344132bb601c78ca3a01 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/91354 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Boolean options are intended to represent generic "Enable"/"Disable" options, but without enum options' extra bloat in the CFR structures. Change-Id: I6c4e44507fc371fc8b693b2289c58eb61ac84aa8 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/91355 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Boolean options are intended to represent generic "Enable"/"Disable" options, but without enum options' extra bloat in the CFR structures. In this case, the callback function already treated the option as if it were a boolean option, which likely only worked by chance. Change-Id: Ic4b86c45e4837fcdb30cf594bb7e30400864e77e Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/91356 Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Introduce a new directory structure src/soc/intel/common/feature/ for sharing SoC-specific code across Intel SoC generations to reduce code duplication. Unlike the common block code (src/soc/intel/common/block/) which is intended for reusable IP blocks, the feature code is for SoC-specific functionality that is similar (but not identical) across multiple generations. Platform-specific differences are handled through configuration options or platform-specific macros. This commit: - Creates src/soc/intel/common/feature/ directory - Adds feature/Kconfig defining SOC_INTEL_COMMON_FEATURE - Adds feature/Makefile.mk to build subdirectories - Updates src/soc/intel/common/Kconfig.common to source feature/Kconfig - Updates src/soc/intel/common/Makefile.mk to include feature/ subdirs - Documents the common code directory structure in Documentation/soc/intel/code_development_model/code_development_model.md Change-Id: Idb842376a0a785a6439eeeb5a3a934d0bc575b09 Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/91360 Reviewed-by: Bora Guvendik <bora.guvendik@intel.corp-partner.google.com> Reviewed-by: Jakub "Kuba" Czapiga <czapiga@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Pranava Y N <pranavayn@google.com>
This patch introduces a common UART device list implementation that eliminates duplication across multiple Intel SoC platforms. Instead of maintaining nearly identical uart.c files in each platform directory, this common driver uses platform-specific macros to define UART device function numbers. The common implementation expects each platform to define the following macros in their soc/pci_devs.h header: - PCI_DEVFN_UART0 - PCI_DEVFN_UART1 - PCI_DEVFN_UART2 This approach maintains platform flexibility while reducing code duplication and simplifying maintenance. The driver is compiled across all stages (bootblock, verstage, romstage, postcar, ramstage, smm) to support various UART usage scenarios. Change-Id: Iba82a2fe24dd9ccf704e4a0fadc481b63662b94d Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/91241 Reviewed-by: Kim, Wonkyu <wonkyu.kim@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Pranava Y N <pranavayn@google.com>
Remove platform-specific uart.c and switch to the common UART device list driver. This eliminates 18 lines of duplicate code. The Alder Lake uart.c simply defined uart_devices[] array with PCH_DEVFN_UART* macros. The common driver now handles this using the PCI_UART_DEVFNn macro defined in pci_devs.h. This commit: - Adds PCI_DEVFN_UART* aliases pointing to PCH_DEVFN_UART* for naming consistency with common code - Selects SOC_INTEL_COMMON_FEATURE and SOC_INTEL_COMMON_FEATURE_UART_DEVICES in Kconfig - Removes uart.c and updates Makefile.mk Change-Id: Iafd4881c44dd9ccf7e204378bbafafbd1c884db0 Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/91242 Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Remove platform-specific uart.c and switch to the common UART device list driver. This eliminates duplicate code. The pantherlake uart.c simply defined uart_devices[] array. The common driver now handles this using the PCI_UART_DEVFN macro defined in pci_devs.h. This commit: - Selects SOC_INTEL_COMMON_FEATURE and SOC_INTEL_COMMON_FEATURE_UART_DEVICES in Kconfig - Removes uart.c and updates Makefile.mk Change-Id: I59443ece21bc45c8b6986fdd2bc24dd9ccf7a543 Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/91244 Reviewed-by: Kim, Wonkyu <wonkyu.kim@intel.com> Reviewed-by: Pranava Y N <pranavayn@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
…L.3515.03 Update Wildcatlake FSP headers to align with the FSP version WCL.3515.03. BUG=b:475358197 TEST=Build the ocelot CB with the latest header changes. Change-Id: I1232523e662d91cf43e7ed6bcc4fbefeaf8447e9 Signed-off-by: Sowmya V <v.sowmya@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/90753 Reviewed-by: Pranava Y N <pranavayn@google.com> Reviewed-by: Avi Uday <aviuday@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Increase the logo_bottom_margin from 100 to 200 in the display_logo configuration if FRAMEBUFFER_SPLASH_TEXT Kconfig is enabled. This adjustment ensures the OEM footer logo and associated splash text are rendered higher on the screen, improving visibility and alignment with updated UX requirements. BUG=None TEST=Boot MediaTek device and verify the splash text is 200px from the screen bottom edge as expected. Change-Id: I490e50e200dfffedf24cb30fe0ca6ea6ae037d3d Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/91383 Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Be consistent when printing the channel assignment, and use unsigned printf specifiers since the values themselves are unsigned. Change-Id: I66b93233707dec73dc7a25423789a24770ac678f Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/91376 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Benjamin Doron <benjamin.doron00@gmail.com>
DDR frequency (in MHz) was doubled for no reason, then doubled again to
convert it to MT/s. Moreover, the calculations assume a reference clock
of 133 MHz, but a 100 MHz reference clock also exists.
Add two functions: `is_100_mhz_refclk()` to check whether the reference
clock is 100 MHz, and `get_ddr_freq_mhz()` to get the DDR frequency, in
MHz. Use both functions in `report_memory_config()` to show the correct
DDR ref. clock and frequency, and use one in `setup_sdram_meminfo()` so
that SMBIOS tables contain the correct memory speed.
Tested on ASRock Z97 Extreme6 with four DDR3-1600 sticks, DDR frequency
is correctly reported as 800 MHz with either reference clock frequency:
Default 133 MHz reference clock:
memcfg DDR3 ref clock 133 MHz
memcfg DDR3 clock 800 MHz
After forcing 100 MHz ref clock for 800 MHz (edit NRI's `init_mpll.c`):
memcfg DDR3 ref clock 100 MHz
memcfg DDR3 clock 800 MHz
Also, SMBIOS type 17 correctly reports memory speeds of 1600 MT/s:
$ sudo dmidecode --type 17 | grep -i speed
Speed: 1600 MT/s
Configured Memory Speed: 1600 MT/s
Speed: 1600 MT/s
Configured Memory Speed: 1600 MT/s
Speed: 1600 MT/s
Configured Memory Speed: 1600 MT/s
Speed: 1600 MT/s
Configured Memory Speed: 1600 MT/s
It is expected that behaviour using either MRC binary is the same since
the `MC_BIOS_REQ` and `MC_BIOS_DATA` registers have to be programmed in
order for the DDR clock to start running. The decision to test with NRI
is because one can easily change the chosen reference clock to 100 MHz.
Resolves: https://ticket.coreboot.org/issues/624
Change-Id: Idead9cd55b453d3ff4695c977dee763ff50830f8
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91375
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Benjamin Doron <benjamin.doron00@gmail.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
The `intel_early_me_init_done()` function prints the ME status. In order to see the ME status once in all paths, have the aforementioned function only call `intel_early_me_status()` before handling a reset request. Change-Id: I42ad1b25889a21047b7cf55e7940293e73794d8b Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/91374 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Benjamin Doron <benjamin.doron00@gmail.com> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
For most targets it's known if the CPU supports alternative SMRR registers or not. Only on model_6fx runtime detection is necessary. On all platforms this allows the compiler to optimize the code and thus shrink the code size if alternative SMRR aren't supported. TEST=On Lenovo X220 the ramstage is 308 bytes smaller. Change-Id: I3a965d142f79ad587b8cedc9b4646b05e2a45f8b Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/91014 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Use existing define for SMRR and PMRR support instead of redefining it in various places. TEST=No functional change, thus untested. Change-Id: Ie366a9d695800acd9713bd4e8393201a1f0a5ab2 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/91015 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Move the defines for PCI register SMM_FEATURE_CONTROL to the header soc/pci_devs.h like it's done on other server platforms as well. While on it add BIT1 that will be used in the following commit. TEST=Not a function change, thus untested. Change-Id: Ib05bb129f069ab1a6f4752a2dac829b3b7b41ec9 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/91016 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Remove platform-specific uart.c and switch to the common UART device list driver. This eliminates duplicate code. The meteorlake uart.c simply defined uart_devices[] array. The common driver now handles this using the SOC_UART_DEVFN(n) macro defined in pci_devs.h which uses token concatenation to map to platform-specific PCI_DEVFN_UARTn definitions. This commit: - Selects SOC_INTEL_COMMON_FEATURE and SOC_INTEL_COMMON_FEATURE_UART_DEVICES in Kconfig - Removes uart.c and updates Makefile.mk Change-Id: Ic791eaa2521a44aba330e149fb0185094dd9ccf7 Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/91243 Reviewed-by: Kim, Wonkyu <wonkyu.kim@intel.com> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Change-Id: Ic30bec272e82535f6f606033c3ba512662cb2c8b Signed-off-by: Jeremy Soller <jackpot51@gmail.com>
These values were taken from alderlake. Change-Id: Ib790c7d52748156b25bad423ed082c1b51a33550 Signed-off-by: Jeremy Soller <jackpot51@gmail.com>
Intel introduced a new UPD specifically for setting the HDA subsystem ID in FSP-M. Using SiSsidTablePtr in FSP-S no longer works as it will be locked with a default value of 0 by that point. Tested on Clevo V560TU with MTL FSP 4122.12 (0D.00.A8.20). TEST=PCI config space for HDA device has subsystem ID set. Change-Id: I5e668747d99b955b0a3946524c5918d328b8e1d3 Signed-off-by: Tim Crawford <tcrawford@system76.com>
Change-Id: Id7f4373989dffe8c3bc68a034f59a94d2160dd15 Signed-off-by: Jeremy Soller <jeremy@system76.com>
The Bonobo has 2 AMPs: one for the speakers and one for the subwoofer. Smart AMP data was collected using a logic analyzer connected to the IC during system start on proprietary firmware. This data is then used to generate a C file [1]. [1]: https://github.com/system76/smart-amp Change-Id: I5389a9890563ebd3adb20096b6225f474bc006f9 Signed-off-by: Tim Crawford <tcrawford@system76.com>
This config is not available in coreboot FSP headers, but is required for USB3 to work correctly. Change-Id: I253c7b6b9fe67e251f6ba88d8176c7058292de0a Signed-off-by: Tim Crawford <tcrawford@system76.com>
The Bonobo has been updated with a Thunderbolt 5 controller (Barlow Ridge). Identified chip changes from the schematics: - JHL8540_MP -> JHL9580_QS - TPS65994BF -> TPS65994BH - IT5570E-128 -> IT5570E-256 Change-Id: I784e489cdd034febeaaac0182ab5b4fe672381ec Signed-off-by: Tim Crawford <tcrawford@system76.com>
The Meerkat 9 is an Intel Meteor Lake-H based small form factor desktop computer based on the Asus NUC-155H R2. Change-Id: I37a0b808cf383379b8e284831644c824c0d4817e Signed-off-by: Jeremy Soller <jeremy@system76.com> Signed-off-by: Tim Crawford <tcrawford@system76.com>
Change-Id: I202c0607c2cdac1df59f42fb41735704dd5bd95c Signed-off-by: Jeremy Soller <jeremy@system76.com> Signed-off-by: Tim Crawford <tcrawford@system76.com>
Change-Id: I4b07846c404eb93ab4baf0a78a4bbffcc5d8afca Signed-off-by: Tim Crawford <tcrawford@system76.com>
Add a driver for laptops with NVIDIA Optimus (hybrid) graphics. The driver provides ACPI support for dynamically powering on and off the GPU, NVIDIA Dynamic Boost support, and a function for enabling the GPU power in romstage. References: - DG-09845-001: NVIDIA GN20/QN20 Hardware Design Guide - DG-09954-001: NVIDIA GN20/QN20 Software Design Guide Change-Id: I2dec7aa2c8db7994f78a7cc1220502676e248465 Signed-off-by: Jeremy Soller <jeremy@system76.com> Signed-off-by: Tim Crawford <tcrawford@system76.com>
Change-Id: I4ca91ff631dd4badbfba72e69651f03753323a54 Signed-off-by: Tim Crawford <tcrawford@system76.com>
The HX boards, using PCH-S, use a discrete Thunderbolt device (Intel Maple Ridge), as opposed to a built-in one like the boards using PCH-P. Fixes Thunderbolt on RPL-HX boards using the Maple Ridge controller. Change-Id: I53d18f3ec5a084431e1113782c791bcb42728350 Signed-off-by: Tim Crawford <tcrawford@system76.com>
The newer batch of these boards do not de-assert VW PLTRST# on S3 resume, causes the units to not power on in the EC code. Switch them to S0ix by default, but leave S3 available. Change-Id: I95337c1391102db9e020e82bdd938659c1a4f905 Signed-off-by: Tim Crawford <tcrawford@system76.com>
Since these boards will use S0ix they need to leave CSME enabled for the CPU to reach C10. Change-Id: I70c908402c9964508bb9c439d48d24773f5a35ab Signed-off-by: Tim Crawford <tcrawford@system76.com>
Change-Id: I5873e2bd61b76331ed88023260ece3ab9c3c3eff Signed-off-by: Tim Crawford <tcrawford@system76.com>
Disable feature as it causing GPU to fail under load, such as running FurMark as part of Phoronix Test Suite. Change-Id: I0b04cbd8fbab2ba8ff38281b91c83aa94c7e1bf1 Signed-off-by: Tim Crawford <tcrawford@system76.com>
Change-Id: I291a806912f967fa797b5fae77c5fff6610733bf Signed-off-by: Tim Crawford <tcrawford@system76.com>
Change-Id: Ifeec06c1c79216afe840eff2d9cb91a6d4d8d5a3 Signed-off-by: Tim Crawford <tcrawford@system76.com>
- Add more inline docs - Add `_STA` method - Update field names to better match names from Clevo dumps/DG samples - Add fields for v2.4 (unimplemented) - Add `TGPA` field for `UPDATE_DYNAMIC_PARAMS` - Match proprietary behavior for "Set Controller Status" - Add objects for disabling boost on AC/DC - Add debug logs for unimplemented functions Change-Id: I2a8d791198e18fca6eb907e62f92143fbe1e3962 Signed-off-by: Tim Crawford <tcrawford@system76.com>
Change-Id: I9e5525d4197953c430325d813ee20d980dddab63 Signed-off-by: Jeremy Soller <jackpot51@gmail.com>
Change-Id: Iea09f90a6e53035ce379afa6d7dd4ad3a83333c6 Signed-off-by: Jeremy Soller <jackpot51@gmail.com>
Change-Id: Iafb7d137332ee0668dfc1a3cf47a4d881b8cdfb8 Signed-off-by: Jeremy Soller <jackpot51@gmail.com>
Change-Id: I5f0b8cf65446b275deb5207d344fde97da1dc833 Signed-off-by: Tim Crawford <tcrawford@system76.com>
Fixes: c0ba116 ("soc/intel/adl,mtl: Use channel 0 only for memory down in mixed topo") Change-Id: I56e7d51b4a06519376d8fe7a345bb434c6f1a24a Signed-off-by: Tim Crawford <tcrawford@system76.com>
The GPU sometimes crashes when GPU Boost is used. Disable the feature until root cause can be identified and resolved. Change-Id: Ib3624c1241921268627cfc85b4427bc9891fa0a3 Signed-off-by: Tim Crawford <tcrawford@system76.com>
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Draft until booting. Based on latest upstream commit to have newest pantherlake soc code