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fix: make PLL2M dynamic to keep VCO=800MHz for any HSE frequency (closes #11594)#11596

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fix: make PLL2M dynamic to keep VCO=800MHz for any HSE frequency (closes #11594)#11596
daijoubu wants to merge 2 commits into
iNavFlight:maintenance-9.xfrom
daijoubu:fix/11594-pll2-dynamic-m-divider

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@daijoubu daijoubu commented May 28, 2026

Summary

PLL2M was hardcoded to 5, which assumes HSE = 8 MHz (giving VCO = 800 MHz).
On KakuteH7Wing (HSE = 16 MHz), VCO = 16/5 * 500 = 1600 MHz, far exceeding
the STM32H7 specification. This caused the SDMMC kernel clock (PLL2R = 4)
to run at 400 MHz instead of the expected 200 MHz.

Fix

Compute PLL2M from HSE_VALUE (same formula as PLL1M) and reduce PLL2N
from 500 to 400, pinning VCO to 800 MHz for any HSE frequency:

  • HSE=8: M=4, N=400 → VCO=800 MHz
  • HSE=16: M=8, N=400 → VCO=800 MHz

Testing

Build: KAKUTEH7WING Release — 0 errors, 0 warnings
SD card test 1 (detection): PASS — card detected, filesystem Ready
SD card test 2 (write): 4 MB written in 60s at 68 KB/s, no errors

Closes #11594

Risk

Low — only affects H7 targets with HSE ≠ 8 MHz (currently only
KAKUTEH7WING at 16 MHz). For all standard 8 MHz HSE targets the
VCO remains 800 MHz (M goes from 5 to 4, N from 500 to 400).

PLL2M was hardcoded to 5, which assumes HSE = 8 MHz (giving VCO = 800 MHz).
On KakuteH7Wing (HSE = 16 MHz), VCO = 16/5 * 500 = 1600 MHz, far exceeding
the STM32H7 specification. This caused the SDMMC kernel clock (PLL2R = 4)
to run at 400 MHz instead of the required 200 MHz.

Fix: compute PLL2M from HSE_VALUE (same formula as PLL1M) and reduce PLL2N
from 500 to 400, pinning VCO to 800 MHz for any HSE frequency:
  - HSE=8:  M=4, N=400 → VCO=800 MHz
  - HSE=16: M=8, N=400 → VCO=800 MHz

Closes iNavFlight#11594
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github-actions Bot commented May 28, 2026

Test firmware build ready — commit 9570a92

Download firmware for PR #11596

237 targets built. Find your board's .hex file by name on that page (e.g. MATEKF405SE.hex). Files are individually downloadable — no GitHub login required.

Development build for testing only. Use Full Chip Erase when flashing.

With VCO = 800 MHz, PLL2P = 2 gives 800/2 = 400 MHz.
@daijoubu
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Original comment on PLL2P was incorrect at 500 MHz. Standard HSE source is 8 MHz.

  • PLL2M=5, PLL2N=500
  • VCO = 8/5 * 500 = 800 MHz
  • PLL2P = 2 → 800/2 = 400 MHz

@daijoubu daijoubu marked this pull request as ready for review May 29, 2026 00:30
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@daijoubu daijoubu marked this pull request as draft May 29, 2026 05:13
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Accidentally changed PLL2M to give a VCO input of 2 MHz instead of 1.6 MHz. Works, but VCIRANGE is now incorrect. Better to shift it back to 1.6 MHz. Will test tomorrow and the update.

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This PR was closed when its branch was deleted during a rebase. The updated fix has been opened as #11603.

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